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Introduction to Processor SDK RTOS Frequently Asked Questions (FAQ)

Date:
January 26, 2017

Duration:
05:34
This video provides an introduction to the Wiki article where you can find answers when developing real time software using the Processor SDK for RTOS

Sitara™ Processors: Running TI-RTOS on the ARM Cortex™-M4 Processor

Date:
October 21, 2016
This module provides an introduction to the dual-core ARM Cortex-M4 Image Processing Unit (IPU) Subsystem, including the memory map, cache maintenance and control using UNICACHE and MMU, and bit banding. It also provides an overview of how to create, load, and run applications on the Cortex-M4 and provides an IVA-HD application use case example.

OpenCL™ & OpenMP® Offload on Sitara™ AM57x Processors

Date:
October 14, 2016
This module discusses how to leverage OpenCL and OpenMP Offload to dispatch processing to the C66x DSPs on Sitara AM57x processors.

Introduction to the Sitara™ AM57x Processor Industrial Software Development

Date:
September 15, 2016
This training provide an overview of the AM57x Industrial SDK architecture, decribes the ISDK capabilities and supported protocols, and shows how Sitara AM57x processors and the ISDK support an Industry 4.0 application. 

Ethernet System Hardware on Sitara AM-Class Processors

Date:
June 30, 2016
This module provides a system perspective of the Ethernet interface on Sitara AM-class processors, from understanding the MAC-PHY relationship to discussing elements such as interface clocking, PHY modes, MAC-to-MAC, and expected scope captures of the MDIO bus and signal bus. It also addresses Ethernet interface layout considerations, including length matching, reference planes, and via spacing.  Overall, this training will develop an understanding of hardware design, as well as common hardware debugging procedures for both board bring up and product development.

Sitara™ Processors Building Blocks for PRU Development: Designing a PRU Application

Date:
May 25, 2016
The Programmable Real-Time Unit (PRU) is a small processor that is tightly integrated with an IO subsystem, offering low-latency control of IO pins on TI’s SoC devices including the AM335x, AM437x, and AM57x Sitara Processors. The PRU is customer-programmable and can be used to implement simple and flexible control functions, peripherals, and state machines that directly access IO pins of the device, as well as can communicate with the application cores. This session provides an overview of the PRU application design process, from application definition and system flow planning to how to architect firmware and estimate timing/cycle requirements. An example application is used to illustrate the decision-making process throughout the lesson.

Sitara™ Processors: Programmable Real-Time Unit (PRU) Compiler Tips & Tricks

Date:
March 30, 2016
This presentation provides tips and tricks for using the Programmable Real-Time Unit (PRU) C/C++ Compiler, including recommendations.

Sitara™ Processors Building Blocks for PRU Development: Hardware

Date:
March 30, 2016
The Programmable Real-Time Unit (PRU) is a small processor that is tightly integrated with an IO subsystem, offering low-latency control of IO pins on TI’s SoC devices including the AM335x, AM437x, and AM57x Sitara Processors. The PRU is customer-programmable and can be used to implement simple and flexible control functions, peripherals, and state machines that directly access IO pins of the device, as well as can communicate with the application cores. This session provides an overview of PRU hardware, including how PRU subsystem components fit into the TI SoC architecture, a description of the PRU submodule functions, and an introduction to example PRU applications.

Sitara™ Processors Building Blocks for PRU Development: Firmware

Date:
March 30, 2016
The Programmable Real-Time Unit (PRU) is a small processor that is tightly integrated with an IO subsystem, offering low-latency control of IO pins on TI’s SoC devices including the AM335x, AM437x, and AM57x Sitara Processors. The PRU is customer-programmable and can be used to implement simple and flexible control functions, peripherals, and state machines that directly access IO pins of the device, as well as can communicate with the application cores. This session provides an overview of PRU firmware development, including the PRU Code Generation Tools (CGT) provided by TI, how to use the PRU register header files, and various options for development and debug both inside and outside of Code Composer Studio (CCS).
9 Results