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72 Results

How to configure the RX NCOs using the AFE74xx EVM

Date:
March 4, 2019

Duration:
05:46
Learn how to configure the RX NCO settings, in single band mode, using the AFE74xx EVM.

How to configure the AFE74xx in Mode 4 using an external clock

Date:
March 4, 2019

Duration:
05:04
Learn how to program the AFE74xx EVM using an external clock.

Configure the TX NCOs using the AFE74xx EVM

Date:
March 4, 2019

Duration:
04:11
Learn how to configure the TX NCOs in single band mode, using the AFE74xx EVM.

Hardware setup for external clock operation with the AFE74xx EVM

Date:
March 4, 2019

Duration:
03:10
Learn how to set up the hardware to configure the AFE74xx EVM, in mode 4, using an external clock.

How to configure the AFE74xx EVM in transceiver mode

Date:
March 4, 2019

Duration:
02:03
Learn how to operate the AFE74xx EVM in transceiver mode.

How to configure the AFE74xx ADC in Mode 4 using the internal PLL

Date:
March 1, 2019

Duration:
02:33
Learn how to capture with the ADC in mode 4 with the AFE74xx EVM.

How to configure the AFE74xx DAC in Mode 4 using the internal PLL

Date:
March 1, 2019

Duration:
04:55
Learn how to configure the DAC in mode 4 with the AFE74xx EVM

Hardware setup for internal PLL operation with the AFE74xx EVM

Date:
March 1, 2019

Duration:
02:42
Learn how to set up the hardware for internal PLL clock operation.

Selecting the right configuration mode with the AFE74xx EVM

Date:
March 1, 2019

Duration:
03:27
Learn how to select the desired mode to configure the AFE.

Getting started with the AFE74xx RF-sampling transceiver

Quickly evaluate the AFE7444 and/or AFE7422 RF-sampling transceiver with this series of how to videos.

Synchronization of High Speed Multichannel JESD204B Compliant Clocks Part 3

Date:
July 25, 2018

Duration:
11:22
Learn about the high channel count clocking solution.

Synchronization of High Speed Multichannel JESD204B Compliant Clocks Part 2

Date:
July 25, 2018

Duration:
09:56
Learn about the JESD204B compliant high speed multichannel synchronized clocking architecture

How to synchronize high speed multi-channel clocks?

Modern high speed end equipment's like oscilloscope, 5G wireless communication tester and RADAR requires multichannel transceiver system. The biggest challenge is to provide the high frequency, low phase noise, multiple synchronized clocks to each transceiver's data converters and local oscillator. This training will explain how to synchronize the high speed multi-channel clocks and expand for high channel count clocks requirement.

Synchronization of High Speed Multichannel JESD204B Compliant Clocks Part 1

Date:
July 17, 2018

Duration:
07:50
Learn about the high speed multi-channel clocking requirements and challenges.

Webinar - What you need to know about Clock Generators, Buffers and RF Synthesizers

Date:
June 27, 2018

Duration:
54:18
Want to learn more about Clock Generators and Buffers ? You're in the right place!

LMX8410LEVM Walkthrough

Date:
April 10, 2018

Duration:
05:47
In this video, we review the LMX8410LEVM kit, equipment & software, hardware setup, software setup, outputs and optional modifications.
Optimize Your RF Sampling ADC Receiver Performance with the Frequency & Sample Rate Planning Calculator

Optimize Your RF Sampling ADC Receiver Performance with the Frequency & Sample Rate Planning Calculator

Date:
April 6, 2018

Duration:
34:18
This video will go over what ADC SFDR's are, explain the concept of frequency planning and provide tools to help with RF sampling design. 

TI Solutions for Clock and Timing

Date:
December 7, 2017

Duration:
15:08
Learn about solutions to common aerospace and defense design challenges to help you simplify designs and improve performance.

Get Your Clocks in Sync for JESD204B Data Converters

Date:
September 6, 2017

Duration:
19:17
This video will explore a reference design that shows how to synchronize multiple high-speed JESD204B data converters.

Get Your Clocks in Sync: Hardware Setup

Date:
August 14, 2017

Duration:
02:31
This video demonstrates DEV_CLK skew between two clock outputs of the clocking reference design and the analog channel to channel skew between 2 ADC12DJ3200EVMs
72 Results
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