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23 Results

TI Precision Labs - Clocks and Timing: System Design Considerations

The videos in this series will discuss distributed vs. centralized clock tree, synchronous vs. free-running designs and other selection criteria requirements to help narrow down a clock tree solution. We will discuss other design considerations including frequency planning, spurious and EMI noise reduction techniques, system clock optimization/tuning and clocking for JESD204 B/C systems.

Clocking Solutions for High Speed Multi-Channel Applications

Explore clocking solutions for a variety of high speed multi-channel applications. 

Synchronization of High Speed Multichannel JESD204B Compliant Clocks Part 3

Date:
July 25, 2018

Duration:
11:22
Learn about the high channel count clocking solution.

Synchronization of High Speed Multichannel JESD204B Compliant Clocks Part 2

Date:
July 25, 2018

Duration:
09:56
Learn about the JESD204B compliant high speed multichannel synchronized clocking architecture

How to synchronize high speed multi-channel clocks?

Modern high speed end equipment's like oscilloscope, 5G wireless communication tester and RADAR requires multichannel transceiver system. The biggest challenge is to provide the high frequency, low phase noise, multiple synchronized clocks to each transceiver's data converters and local oscillator. This training will explain how to synchronize the high speed multi-channel clocks and expand for high channel count clocks requirement.

Synchronization of High Speed Multichannel JESD204B Compliant Clocks Part 1

Date:
July 17, 2018

Duration:
07:50
Learn about the high speed multi-channel clocking requirements and challenges.

Webinar - What you need to know about Clock Generators, Buffers and RF Synthesizers

Date:
June 27, 2018

Duration:
54:18
Want to learn more about Clock Generators and Buffers ? You're in the right place!

TI Solutions for Clock and Timing

Date:
December 7, 2017

Duration:
15:08
Learn about solutions to common aerospace and defense design challenges to help you simplify designs and improve performance.

Get Your Clocks in Sync for JESD204B Data Converters

Date:
September 6, 2017

Duration:
19:17
This video will explore a reference design that shows how to synchronize multiple high-speed JESD204B data converters.

Get Your Clocks in Sync: Hardware Setup

Date:
August 14, 2017

Duration:
02:31
This video demonstrates DEV_CLK skew between two clock outputs of the clocking reference design and the analog channel to channel skew between 2 ADC12DJ3200EVMs

Get Your Clocks in Sync: Software Setup

Date:
August 7, 2017

Duration:
04:20
This video demonstrates the software setup of the Multi-Channel JESD204B 15 GHz Clocking Reference Design for DSO, Radar and 5G Wireless Testers

Local oscillator and GHz clocks requirements in Radio applications systems with LMX2594

This training series discusses the key requirements of local oscillator in microwave/RF and GHz clocks in  radio applications. The topics covered establish the key relationships between the requirements of a signal source and their impact in a radio system. After this training, you will be armed with the ability to understand the system requirements of your customer and how they pertain to a signal source so you can engage with your customer in a very meaningful way.

Advanced Phase Synchronization Capabilities with Multiple RF PLLs using TI's LMX2594

Advanced Phase Synchronization Capabiliites with Multiple RF PLLs using TI's LMX2594

Date:
April 19, 2017

Duration:
07:08
Watch Nadeem demonstrate advanced phase synchronization capabilities with multiple RF PLLs using TI's high performance LMX2594.

LMX2592 high performance RF Synthesizer from TI

Date:
April 13, 2016

Duration:
04:57
Watch Dean get high performance without the complexity of discrete components with TI's LMX2592 high performance RF Synthesizer

Engineer It: How to ehance accuracy in radar applications

Date:
April 13, 2016

Duration:
13:54
Simon explains how to enhance accuracy in radar applications using TI's RF Synthesizers

Engineer It: How to design with excellent PLL & VCO noise performance

Date:
April 12, 2016

Duration:
18:18
Simon shows how to optimize your system design with easy design tips to gain excellent PLL & VCO noise performance

Engineer It: How to control synthesizer phase noise

Date:
November 13, 2015

Duration:
08:37
A demonstration of how to analyze for synthesizer phase noise in your application

LMX2492: 14 GHz Frac-N PLL with ramp/chirp capabilities

Date:
November 8, 2014

Duration:
07:31
Simon demonstrates the ramping features of the LMX2492, a feature-rich 14 GHz fractional-N PLL with advanced frequency modulation, very low phase noise perform

LMX2541 - Fractional Spur Performance

Date:
November 2, 2014

Duration:
14:17
Part 4 of 5 presentations on the LMX2541, this video discusses: * Fractional spurs * Impact of fractional spurs on system performance

LMX2541 - Simulation Using TIs Clock Design Tool

Date:
November 2, 2014

Duration:
10:07
This video discusses: LMX2541 simulation using TI's Clock Design Tool
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