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Achieving Ultra-Low Power design in Always-On and Power Cycled applications with Nanopower Op Amps and Nanotimers

Date:
December 7, 2016

Duration:
37:10
How can you implement Texas Instruments nanopower operational amplifiers and nanotimers into your Always On design? Watch this on-demand training to find out.
Precision Top

TI Precision Labs

TI Precision Labs (TIPL) is the most comprehensive online classroom for analog signal chain designers. From foundational knowledge to advanced concepts, our logical, sequenced and comprehensive teaching approach is both intuitive and practical. The training series, which includes videos and downloadable reference materials, will deepen the technical expertise of experienced engineers and accelerate the development of those early in their career.

TI Precision Labs - Clocks and Timing

Develop your clocks and timing expertise with our comprehensive curriculum that ranges from introductory to advanced topics from key terminology to design considerations. Our on-demand courses and tutorials pair theory and applied exercises to deepen the technical expertise of experienced engineers and accelerate the development of those early in their careers. 

New content will continue to be added to this series so be sure to check this page for the latest clock and timing lessons!

TI Precision Labs - Clocks and Timing: Introduction

This series of videos gives an overview of clock and timing product types with a high-level discussion of architecture, functionality and features for each. The discussion will center around key performance metrics of Oscillators, Clock Buffers, Jitter Cleaners, PLL's, Network Synchronizers will highlight the key parameters and specifications. Applications case examples and tradeoffs between different clock tree building blocks will be presented to illustrate what type of product function is best suited to meet individual system needs.

TI Precision Labs - Clocks and Timing: Frequency Planning Part 2

Date:
June 27, 2020

Duration:
07:41
Frequency planning part 2 – mitigating spurs and crosstalk

TI Precision Labs - Clocks and Timing: Phase Lock Loop Fundamentals

This video series will explain the building blocks for Phase Lock Loops (PLL's) such as VCO’s, integer and fractional N frequency dividers, phase detectors and charge pumps. We will provide detailed examples of loop filter design and theory along with the effects of discrete sampling and multiple loops on PLL transient response.

TI Precision Labs - Clocks and Timing: System Design Considerations

The videos in this series will discuss distributed vs. centralized clock tree, synchronous vs. free-running designs and other selection criteria requirements to help narrow down a clock tree solution. We will discuss other design considerations including frequency planning, spurious and EMI noise reduction techniques, system clock optimization/tuning and clocking for JESD204 B/C systems.

TI Precision Labs - Clocks and Timing: PLL Transient Response

Date:
December 24, 2019

Duration:
10:41
This training video discusses the PLL transient response including both VCO calibration and analog lock time.

TI Precision Labs - Clocks and Timing: Systems Overview

Date:
December 31, 2019

Duration:
12:48
Introduction to Clock and Timing Systems

TI Precision Labs - Clocks and Timing: EMI Noise Reduction Techniques

Date:
June 29, 2020

Duration:
08:53
Common clock design techniques for reducing EMI.

TI Precision Labs - Clocks and Timing: Frequency Planning

Date:
December 3, 2019

Duration:
10:25
This video will discuss clock generator basics and frequency calculation.

TI Precision Labs - Clocks and Timing: Clocking JESD204B/C Systems

Date:
June 30, 2020

Duration:
10:07
Clocking JESD204B or JESD204C systems.

TI Precision Labs - Clocks and Timing: Noise in Clock and Timing Systems

This series of videos will cover topics around noise in Clock and Timing systems in both time and frequency domains. Subjects include definitions, characteristics and sources of jitter, phase noise figures of merit and the relationship to jitter. We will analyze system-level impairments such as excessive jitter/phase noise and PLL spurious noise for cause and effect by simulation and direct measurement examples.

TI Precision Labs - Clocks and Timing: PLL Phase Noise Figures of Merit

Date:
December 24, 2019

Duration:
08:14
This training module is the first of two parts on the PLL (Phased Locked Loop) building blocks. It focuses on the VCO, N Divider, and Outputs.
TIPL clocking JESD204B training

TI Precision Labs - Clocks and Timing: Jitter and Phase Noise Definition

Date:
January 2, 2020

Duration:
08:24
In this module, we will explore definitions of the different types of jitter as well as some of the system level impairments caused by excessive jitter.

TI Precision Labs - Clocks and Timing: Phase Lock Loop Building Blocks Part 2

Date:
December 31, 2019

Duration:
08:13
This training module is the continuation of part one on the PLL (Phased Locked Loop) building blocks. It focuses on the VCO, N Divider, and Outputs.

TI Precision Labs - Clocks and Timing: Phase Lock Loop Building Blocks Part 1

Date:
December 24, 2019

Duration:
10:47
This training module is the first of two parts on the PLL (Phased Locked Loop) building blocks. It focuses on the VCO, N Divider, and Outputs.

TI Precision Labs - Clocks and Timing: RF Phase Lock Loop (PLL) and Synthesizer Key Parameters

Date:
December 31, 2019

Duration:
11:28
This video discusses the key parameters and specifications in RF Phase Lock Loop (PLL) and synthesizers.

Utilizing JESD204B interface in low cost applications

Date:
November 8, 2014

Duration:
02:47
Get an overview of the 4-channel, 50-MSPS DEV-ADC34J22 evaluation module. The board features TI's ADC34J22 ADC, LMK04828 jitter cleaner and THS4541 fully diffe

Selection of Key Components (ADC, Signal Conditioning Amplifier) for AC Analog Input Module (AIM)

Date:
April 15, 2017

Duration:
12:30
Understand some of the key criteria for selection of ADC, Signal Conditioning Amplifier and TI focus products for AC Analog Input Module.
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