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19 Results

Voltage Regulator Design and Optimization for High-Current, Fast-Slew-Rate Load Transients

Designing to the tight voltage tolerances of today’s modern central processing units and field programmable gate arrays (FPGAs) is becoming more difficult as their current draw increases and becomes more dynamic. Getting the correct output capacitance mix to ensure first-time power-delivery success is no small feat with >100-A steps and slew rates in excess of 100 A/µs. Standard point-of-load design techniques no longer hold true; we need new methods to choose the output capacitance.

Reduce design risk for Low Earth Orbit satellites and other New Space applications

When: October 8, 2019 2:00 pm
What is NewSpace? What does it mean for satellite design? Explore products that meet quality & reliability requirements for short space flights and LEO designs.

Demonstrating the Audio Pre-processing Reference Design for Voice-based Applications on C5517

Date:
July 10, 2017

Duration:
09:37
This video demonstrates the audio pre-processing system reference design for voice-based applications using the C5517 EVM and a linear microphone board.

Understanding Transient Response In the Time and Frequency Domain

Date:
February 10, 2020

Duration:
05:10
Dive into how a regulator's transient response looks in both time and frequency

DC Load Lines: How They Can Benefit Your Next Design

Date:
February 10, 2020

Duration:
05:04
Get top of the line performance out of your regulator by adding a DC Load Line

Output Capacitor Selection Using a Target Impedance Approach

Date:
February 10, 2020

Duration:
08:24
Study two techniques for selecting output capacitance to meet transient specs

DSP Breaktime, Episode Three

Date:
May 14, 2015

Duration:
07:41
Join us for the latest episode of DSP Breaktime, where Mark and Arnon discuss applications where you HAVE to use a DSP, the competitive landscape and more of th

DSP Breaktime, Episode 2

Date:
April 29, 2015

Duration:
07:23
Join us for the latest episode of DSP Breaktime, where Mark and Arnon discuss TI's leadership position in the processor market, real-time processing, radar appl

DSP Breaktime Episode 4

Date:
June 10, 2015

Duration:
06:49
Mark and Arnon are back, and this time they're talking about all things embedded vision. The entire TI DSP portfolio is perfect for this application space, and

DSP Breaktime, Episode Six

Date:
July 31, 2015

Duration:
06:42
In the latest episode, Mark and Arnon discuss the best applications for DSPs, open APIs and why DSPs are so good at math. Also, find out what the guys like to

Save Energy with LED Lighting and Intelligent Sensing

Date:
March 18, 2015

Duration:
43:58
Learn about an intelligent light which is aware of its environment and communicates to other lights using TI’s software and hardware solutions

Demonstrating Voice Triggering and Processing with Cloud Connection to IBM Watson Reference Design

Date:
December 22, 2017

Duration:
09:28
This video demonstrates the voice triggering and processing with cloud connection to IBM Watson reference design using C55x embedded processors.

Voice Processing Tools and Software for K2G and C5517 Designs

Date:
May 3, 2017

Duration:
17:24
This training addresses some of the basic concepts associated with the voice recognition processing technique known as beamforming.

Audio System Hardware with Voice as User Interface

Date:
May 17, 2017

Duration:
24:20
This training identifies the hardware components required to build an application with voice recognition capability.  

C6000 Architecture (2 of 15)

Date:
April 9, 2015

Duration:
01:41:39
This training series provides an in-depth look at C6000 architecture such as cache, using the C compiler/optimizer, EDMA3 and a great intro to the architecture

KeyStone I training: instruction set architecture (ISA)

Date:
March 9, 2015

Duration:
30:57
C66x Instruction Set Architecture describes the differences between the TMS320C674x instruction set architecture and the TMS320C66x instruction set included in the KeyStone CorePac.

C6000 Optimizations - Part 1 (4 of 15)

Date:
April 9, 2015

Duration:
01:09:30
This training series provides an in-depth look at C6000 architecture such as cache, using the C compiler/optimizer, EDMA3 and a great intro to the architecture

C6000 Optimizations - Lab (6 of 15)

Date:
April 9, 2015

Duration:
01:23:28
This training series provides an in-depth look at C6000 architecture such as cache, using the C compiler/optimizer, EDMA3 and a great intro to the architecture

C6000 Optimizations - Part 2 (5 of 15)

Date:
April 9, 2015

Duration:
01:01:04
This training series provides an in-depth look at C6000 architecture such as cache, using the C compiler/optimizer, EDMA3 and a great intro to the architecture
19 Results
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