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334 Results

Introduction to Digital Front End (DFE) for 66AK2L06/TCI6630K2L Processors

Date:
December 2, 2015
This module provides an overview of the Digital Front End (DFE) integrated into 66AK2L06/TCI6630K2L DSP + ARM processors from Texas Instruments.

Multicore Software Development Kit (MCSDK) for KeyStone Devices

Date:
October 1, 2011
This module provides an overview of the multicore SoC software for KeyStone I C66x DSP devices. This module introduces the optimized software components that e

KeyStone I training: network coprocessor (NETCP) overview

Date:
November 9, 2010

Duration:
04:20
Network Coprocessor (NETCP) Overview provides an introduction to the NETCP, which includes the Packet Accelerator (PA), Security Accelerator (SA), and Ethernet Subsystems.

KeyStone I training: fast fourier transform coprocessor (FFTC)

Date:
November 9, 2010

Duration:
25:22
Fast Fourier Transform Coprocessor (FFTC) presents the architecture and features of the FFT Coprocessor.

KeyStone I training: I/O interfaces

Date:
November 9, 2010

Duration:
22:05
I/O Interfaces provides an overview of selected external interfaces on the C66x devices including UART, I2C, SPI, TSIP and EMIF-A.

KeyStone I training: NETCP - security accelerator (SA)

Date:
November 9, 2010

Duration:
15:45
NETCP Security Accelerator (SA)takes a look at the motivation behind the SA, the firmware and low level drivers, as well as a usage case for IPSec encryption and decryption.

KeyStone I training: multicore navigator - packet DMA (PKTDMA)

Date:
November 9, 2010

Duration:
32:16
Multicore Navigator: Packet DMA (PKTDMA) provides a detailed look at the infrastructure and functional aspects of the PKTDMA and provides information on programming PKTDMA through the use of registers and low level drivers.

KeyStone I training: power management

Date:
November 9, 2010

Duration:
24:26
Power Management provides an overview of the C66x power domain topology, power-saving features, power and clocking domains, powers states, and Smart Reflex.

KeyStone I training: introduction to interprocessor communication (IPC)

Date:
November 9, 2010

Duration:
40:28
Introduction to Interprocessor Communication (IPC) provides an overview of the hardware and software that transports data and/or signals between threads of execution in the KeyStone family of C66x multicore devices.

KeyStone I training: multicore navigator - queue manager subsystem (QMSS)

Date:
November 9, 2010

Duration:
28:22
Multicore Navigator: Queue Manager Subsystem (QMSS) provides a detailed look at the functional elements of the QMSS and provides information on programming QMSS through the use of registers and low level drivers.

KeyStone I training: NETCP - packet accelerator (PA)

Date:
November 9, 2010

Duration:
26:36
NETCP Packet Accelerator (PA) takes a look at the motivation behind the PA, the hardware, firmware and low level drivers, as well as a programming use case.

KeyStone I training: turbo decoder co-processor (TCP3D)

Date:
November 9, 2010

Duration:
45:16
Turbo Decoder Co-Processor (TCP3D) provides an overview of TCP3D including key features, modes, drivers, and configuration. Examples are provided.

KeyStone I training: debug overview

Date:
November 9, 2010

Duration:
42:10
Debug Overview introduces the C66x debug features including triggers, statistics, and traces.

KeyStone I training: antenna Interface V2 (AIF2)

Date:
November 9, 2010

Duration:
01:17:03
Antenna Interface V2 (AIF2) provides an overview of the architecture and features of AIF Version 2.
Jacinto 7 processors: heterogeneous processing cores

Jacinto 7 processors: heterogeneous processing cores

Date:
December 30, 2019

Duration:
08:08
An introduction to Jacinto™ 7 processing cores and the features and benefits they provide.

Introduction to C55x Digital Signal Processors

Date:
April 8, 2016
This module provides an introduction to the C55x family of DSPs from Texas Instruments.

66AK2Gx Processors

The 66AK2Gx DSP + ARM processors are designed for automotive and consumer audio, industrial motor control, smart-grid protection and other high-reliability, real-time, compute-intensive applications. This training provides an overview of the device architecture and the processor cores. It also includes training related to voice and audio processing, as well as additional how-to video topics relevant to the EVMK2G evaluation module.

Processor SDK for KeyStone Processors

TI provides key runtime software components and documentation to further ease development. TI’s online training provides an introduction to the Processor SDK and how to use this software to start building applications on TI processors.

66AK2Gx Processor Training Series

Similar to existing KeyStone-based SoC devices, the 66AK2Gx enables both the DSP and ARM cores to master all memory and peripherals in the system. This architecture facilitates maximum software flexibility where either DSP- or ARM-centric system designs can be achieved. 

This curriculum provides an in-depth look at the K2G Processors, Processor SDK-Linux and TI-RTOS, and the Programmable Realtime Unit (PRU).

PRU for 66AK2Gx Processors

The Programmable Real-Time Unit (PRU) is a small processor that is tightly integrated with an IO subsystem, offering low-latency control of IO pins on TI’s SoC devices including the 66AK2Gx, AM335x, AM437x, and AM57x Processors. The PRU is customer-programmable and can be used to implement simple and flexible control functions, peripherals, and state machines that directly access IO pins of the device, as well as can communicate with the application cores.

334 Results
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