eFuses are highly integrated ICs that offer device and system-level protection at the input or the output. Traditionally, complete power path protection circuitry was accomplished with a handful of discrete components – components that can use up to 70% greater board space, introduce unnecessary design hurdles, and potentially slow your time to market if UL recognition is required. Those problems are eliminated with our fully integrated eFuses that include over current, over voltage, reverse polarity and more essential protection functions.

Enterprise data centers. Programmable logic controllers for fully-automated factories. Surround-view systems in your vehicle. What do these applications have common? If a fault impacts the power rails, the impact could be disastrous. Browse our video content or fully tested reference designs to see how our protection devices are solving real-world problems for these spaces.

Or, jump right into our parametric table below to find the eFuse that meets your specification. 

Browse through our beginner resources below if you’re brand new to eFuses or need a refresher on common eFuse functions.

This series of videos will cover topics around noise in Clock and Timing systems in both time and frequency domains. Subjects include definitions, characteristics and sources of jitter, phase noise figures of merit and the relationship to jitter. We will analyze system-level impairments such as excessive jitter/phase noise and PLL spurious noise for cause and effect by simulation and direct measurement examples.

In this video series you will learn the basic fundamentals of instrumentation amplifiers, including what an instrumentation amplifier is and how to use one. These videos will also address the different categories / topologies of instrumentation amplifiers and discuss their benefits and trade-offs.

The videos in this series will discuss distributed vs. centralized clock tree, synchronous vs. free-running designs and other selection criteria requirements to help narrow down a clock tree solution. We will discuss other design considerations including frequency planning, spurious and EMI noise reduction techniques, system clock optimization/tuning and clocking for JESD204 B/C systems.

This video series will explain the building blocks for Phase Lock Loops (PLL's) such as VCO’s, integer and fractional N frequency dividers, phase detectors and charge pumps. We will provide detailed examples of loop filter design and theory along with the effects of discrete sampling and multiple loops on PLL transient response.

This series of videos gives an overview of clock and timing product types with a high-level discussion of architecture, functionality and features for each. The discussion will center around key performance metrics of Oscillators, Clock Buffers, Jitter Cleaners, PLL's, Network Synchronizers will highlight the key parameters and specifications. Applications case examples and tradeoffs between different clock tree building blocks will be presented to illustrate what type of product function is best suited to meet individual system needs.