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53 Results

Synchronizing Multiple JESD204B ADCs

Date:
June 11, 2015

Duration:
03:04
This video illustrates synchronizing two ADC12J4000 ADCs employing JESD204B interface

Introduction to the RF Sampling Architecture

Date:
June 29, 2015

Duration:
03:21
Introduction to the RF sampling architecture in contrast to traditional direct conversion architectures typically used in existing transceivers.

Why RF Sampling

Date:
June 29, 2015

Duration:
03:15
This video specifically addresses the benefits and advantages RF sampling provides that was limited or not possible with existing technology.

RF Sampling: Managing Data Rates

Date:
June 29, 2015

Duration:
03:40
RF Sampling requires fast sampling rates, but the input data rates usually cannot keep pace.  The techniques to mitigate those limitations are addressed.

Selecting a JESD204B Subclass

Date:
July 15, 2015

Duration:
05:14
This video discusses the three subclass modes in the JESD204B standard.  The pros and cons of operating in each subclass is discussed.

High Speed Signal Chain University

High Speed Signal Chain University is your portal to relevant training material on High Speed Data Converters and High Speed Amplifiers including topics related to RF Sampling Converters, JESD204B SerDes standard, and RF Fundamentals.

Understanding Clock Jitter Impact to ADC SNR

Date:
July 21, 2015

Duration:
02:57
This video discusses the sampling clock phase noise performance and how its performance over frequency offset impacts the GSPS ADC SNR performance.

Aerospace & Defense Training Series

The Aerospace and Defense Training Series is your one-stop portal for product specific and system applications training material. Learn about the latest solutions to help you simplify designs, improve performance and meet stringent project requirements. 

ADC32RF45: 1-GHz Bandwidth RF Sampling Solution

Date:
May 15, 2016

Duration:
05:04
The ADC32RF45 is a dual channel, 14-bit, 3-GSPS ADC. This video shows how the ADC32RF45 supports 1-GHz signal bandwidths and beyond for next generation systems.
SEPIC Mode Converters for Automotive LCD Displays Technical Overview

SEPIC Mode Converters for Automotive LCD Displays - Technical Overview

Date:
September 22, 2016

Duration:
20:26
Learn the basics of a DC/DC SEPIC converter, its advantages compared to other DC/DC topologies, and how a SEPIC can help you in your Automotive display design.

How to read an SMD part number

Date:
February 7, 2017

Duration:
04:39
Learn how to read a SMD (Standard Microcircuit Drawing) part number.

Get Your Clocks in Sync: Software Setup

Date:
August 7, 2017

Duration:
04:20
This video demonstrates the software setup of the Multi-Channel JESD204B 15 GHz Clocking Reference Design for DSO, Radar and 5G Wireless Testers

Get Your Clocks in Sync: Hardware Setup

Date:
August 14, 2017

Duration:
02:31
This video demonstrates DEV_CLK skew between two clock outputs of the clocking reference design and the analog channel to channel skew between 2 ADC12DJ3200EVMs

Get Your Clocks in Sync for JESD204B Data Converters

Date:
September 6, 2017

Duration:
19:17
This video will explore a reference design that shows how to synchronize multiple high-speed JESD204B data converters.

How to Select Display SerDes for HMI Systems

Date:
May 8, 2018

Duration:
04:19
How to select proper serializer and deserializer for the signal transmission in the relevant applications of human-machine interface (HMI).

Synchronization of High Speed Multichannel JESD204B Compliant Clocks Part 1

Date:
July 17, 2018

Duration:
07:50
Learn about the high speed multi-channel clocking requirements and challenges.

How to synchronize high speed multi-channel clocks?

Modern high speed end equipment's like oscilloscope, 5G wireless communication tester and RADAR requires multichannel transceiver system. The biggest challenge is to provide the high frequency, low phase noise, multiple synchronized clocks to each transceiver's data converters and local oscillator. This training will explain how to synchronize the high speed multichannel clocks and expand for high channel count clocks requirement.

Synchronization of High Speed Multichannel JESD204B Compliant Clocks Part 2

Date:
July 25, 2018

Duration:
09:56
Learn about the JESD204B compliant high speed multichannel synchronized clocking architecture

Synchronization of High Speed Multichannel JESD204B Compliant Clocks Part 3

Date:
July 25, 2018

Duration:
11:22
Learn about the high channel count clocking solution.

Demonstrating RGB to OLDI/LVDS Display Bridge Reference Design for Sitara™ Processors

Date:
August 3, 2018

Duration:
01:51
This video provides an overview of the OLDI/LVDS display bridge reference design (TIDA-010013) for Sitara processors.
53 Results
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