Creating a Robust Interface Between J6 and FPD-Link .
Designing to the tight voltage tolerances of today’s modern central processing units and field programmable gate arrays (FPGAs) is becoming more difficult as their current draw increases and becomes more dynamic. Getting the correct output capacitance mix to ensure first-time power-delivery success is no small feat with >100-A steps and slew rates in excess of 100 A/µs. Standard point-of-load design techniques no longer hold true; we need new methods to choose the output capacitance.
TI's Jacinto TDA2/TDA3 System-on-Chip (SoC) family offers scalable and open solutions based on a heterogeneous hardware and common software architecture for Advanced Driver Assistance System (ADAS) applications including camera-based front (mono/stereo), rear, surround view and night vision systems in addition to multi-range radar and sensor fusion systems.
This training series provides an overview of the evaluation and development platforms as well as getting started with the software and development tools offered by TI on the Jacinto TDA2/TDA3 processors.
This training series focuses on hardware design for the Multi-channel Audio Serial Port (McASP). Before an engineer gets around to writing software for McASP, it has to be wired up properly. That is the focus of this McASP primer.
This training series introduces the OpenVX framework for heterogeneous compute on TI’s Jacinto™ 7 processors. The first module in this series provides background concepts of OpenVX as well as an example of an OpenVX application. The second module introduces TI’s implementation of the OpenVX standard and demonstrates how it is an ideal fit for application development on TI’s Jacinto™ 7 processors.