In this training series, we demonstrate how to use the PRU-ICSS subsystem on a Sitara processor to interface between multiple SAR ADCs using SPI.
Although motor drives have been around for many years, trends in Industry 4.0 such as TSN, industrial IoT, and functional safety are revolutionizing the role a drive takes in the Smart Factory. Where typically its main function was to drive a motor, a servo drive now must include other features to conform with the needs of Industry 4.0. This paired with the rapid growth of the robotics market has created a need for Smart Servo drives with multi-axis capabilities.
This training series focuses on hardware design for the Multi-channel Audio Serial Port (McASP). Before an engineer gets around to writing software for McASP, it has to be wired up properly. That is the focus of this McASP primer.
TI's Jacinto TDA2/TDA3 System-on-Chip (SoC) family offers scalable and open solutions based on a heterogeneous hardware and common software architecture for Advanced Driver Assistance System (ADAS) applications including camera-based front (mono/stereo), rear, surround view and night vision systems in addition to multi-range radar and sensor fusion systems.
This training series provides an overview of the evaluation and development platforms as well as getting started with the software and development tools offered by TI on the Jacinto TDA2/TDA3 processors.
TI’s AM6x Sitara processor family, along with the Processor SDK, brings unparalleled scalability, reliability, integration, and ease-of-use to the Sitara product line. The new, highly-integrated Sitara AM6x processor family provides industrial-grade reliability, with quad and dual Arm® Cortex®-A53 core variants built to meet the rapidly evolving needs of Industry 4.0 in factory automation and grid infrastructure.
This workshop will support the following products - Tiva-C series, MSP430, C6000 and C28x. If you are an AM335x (ARM Cortex A8) user, almost 100% of what is covered in the workshop applies to this target as well with the exception of interrupts and timers. TI-RTOS is mostly target agnostic, so ANY user of ANY TI platform that supports TI-RTOS will learn a ton about the kernel (SYS/BIOS). Also, any Keystone (C66x) users will be able to learn SYS/BIOS in this workshop using the C6748 LCDK platform.
Creating a Robust Interface Between J6 and FPD-Link .
This training series provides background on embedded systems startup to enable users of the AM3x/AM4x/AM57x Sitara processors to make choices that reduce boot time during system design of a selected processor. It introduces the boot time components of the catalog processors, system, and the Processor Linux Software Development Kit (PLSDK). It provides first steps and capabilities to reduce boot time using the Processor SDK without significant customization. This presentation also gives developers a look beyond just the initialization of the selected OS.
This training presents TI’s ready-to-use EtherCAT masters solutions for Sitara processors. EtherCAT master on Sitara runs on different operating systems, including TI-RTOS and RT Linux. It also runs on the EMAC interfaces (CPSW and PRU ICSS_EMAC) of any Sitara device, including AM57x, AM437x, and AM335x.