This training series discusses the key requirements of local oscillator in microwave/RF and GHz clocks in radio applications. The topics covered establish the key relationships between the requirements of a signal source and their impact in a radio system. After this training, you will be armed with the ability to understand the system requirements of your customer and how they pertain to a signal source so you can engage with your customer in a very meaningful way.
The JESD204B video blog series explores the basic concepts related to the JESD204B SerDes standard in relation to High Speed Data Converter products.
This series explores the new realm of RF sampling converters for use in high frequency, large bandwidth systems.
This series explores advanced topics related to the JESD204B SerDes standard associated with extending the link length and multi-device synchronization.
This series covers general updates on Texas Instruments' high-speed signal chain portfolio.
Explore clocking solutions for a variety of high speed multi-channel applications.
TI Precision Labs (TIPL) is the most comprehensive online classroom for analog signal chain designers. From foundational knowledge to advanced concepts, our logical, sequenced and comprehensive teaching approach is both intuitive and practical. The training series, which includes videos and downloadable reference materials, will deepen the technical expertise of experienced engineers and accelerate the development of those early in their career.
High Speed Signal Chain University is your portal to relevant training material on High Speed Data Converters and High Speed Amplifiers including topics related to RF Sampling Converters, JESD204B SerDes standard, and RF Fundamentals.
For noise-critical portable applications, such as GPS receivers, connectivity, and sensing, power supply designers always had to choose between longer battery run time (from higher efficiency) or higher signal chain performance (from the increased sensor sensitivity possible with a quieter power supply). For line-powered industrial or communications equipment applications, designers have been forced to dissipate significant amounts of power in LDOs to achieve the desired noise performance. Achieving both low noise and high efficiency was impossible.
The videos in this series will discuss distributed vs. centralized clock tree, synchronous vs. free-running designs and other selection criteria requirements to help narrow down a clock tree solution. We will discuss other design considerations including frequency planning, spurious and EMI noise reduction techniques, system clock optimization/tuning and clocking for JESD204 B/C systems.