In this training series, we demonstrate how to use the PRU-ICSS subsystem on a Sitara processor to interface between multiple SAR ADCs using SPI.
Although motor drives have been around for many years, trends in Industry 4.0 such as TSN, industrial IoT, and functional safety are revolutionizing the role a drive takes in the Smart Factory. Where typically its main function was to drive a motor, a servo drive now must include other features to conform with the needs of Industry 4.0. This paired with the rapid growth of the robotics market has created a need for Smart Servo drives with multi-axis capabilities.
This training series focuses on hardware design for the Multi-channel Audio Serial Port (McASP). Before an engineer gets around to writing software for McASP, it has to be wired up properly. That is the focus of this McASP primer.
TI’s AM6x Sitara processor family, along with the Processor SDK, brings unparalleled scalability, reliability, integration, and ease-of-use to the Sitara product line. The new, highly-integrated Sitara AM6x processor family provides industrial-grade reliability, with quad and dual Arm® Cortex®-A53 core variants built to meet the rapidly evolving needs of Industry 4.0 in factory automation and grid infrastructure.
This workshop will support the following products - Tiva-C series, MSP430, C6000 and C28x. If you are an AM335x (ARM Cortex A8) user, almost 100% of what is covered in the workshop applies to this target as well with the exception of interrupts and timers. TI-RTOS is mostly target agnostic, so ANY user of ANY TI platform that supports TI-RTOS will learn a ton about the kernel (SYS/BIOS). Also, any Keystone (C66x) users will be able to learn SYS/BIOS in this workshop using the C6748 LCDK platform.
Creating a Robust Interface Between J6 and FPD-Link .
This training series provides background on embedded systems startup to enable users of the AM3x/AM4x/AM57x Sitara processors to make choices that reduce boot time during system design of a selected processor. It introduces the boot time components of the catalog processors, system, and the Processor Linux Software Development Kit (PLSDK). It provides first steps and capabilities to reduce boot time using the Processor SDK without significant customization. This presentation also gives developers a look beyond just the initialization of the selected OS.
This training presents TI’s ready-to-use EtherCAT masters solutions for Sitara processors. EtherCAT master on Sitara runs on different operating systems, including TI-RTOS and RT Linux. It also runs on the EMAC interfaces (CPSW and PRU ICSS_EMAC) of any Sitara device, including AM57x, AM437x, and AM335x.
Advanced closed-loop control systems for factory, process, and power automation markets require powerful MCU solutions that can interface to variety of industrial communications protocols. As new features and capabilities are added, these protocols may evolve several times during the lifetime of an industrial product. As a result, system providers can benefit from solutions that flexibly support multiple communications protocols and in-service updates without updating hardware.
This training series looks at High Availability Seamless Redundancy (HSR) and Parallel Redundancy Protocol (PRP), which are fundamental to many of the tightly-synchronized, high-reliability systems being built today. HSR and PRP work together or separate to keep systems working even when things break so that power stays on and things keep getting built. Both of them work in the low levels of the Ethernet stack to provide the applications that they serve these fundamental capabilities.
Linux is well-adopted within embedded systems. But debugging Linux system issues can be overwhelming. This training series teaches the techniques of debugging kernel issues that may be encountered in embedded Linux systems. This training series explains the Linux kernel logging system and logging API, illustrates how to locate a particular device driver, and demonstrates how to read kernel oops logs.