This workshop will support the following products - Tiva-C series, MSP430, C6000 and C28x. If you are an AM335x (ARM Cortex A8) user, almost 100% of what is covered in the workshop applies to this target as well with the exception of interrupts and timers. TI-RTOS is mostly target agnostic, so ANY user of ANY TI platform that supports TI-RTOS will learn a ton about the kernel (SYS/BIOS). Also, any Keystone (C66x) users will be able to learn SYS/BIOS in this workshop using the C6748 LCDK platform.
This training series focuses on hardware design for the Multi-channel Audio Serial Port (McASP). Before an engineer gets around to writing software for McASP, it has to be wired up properly. That is the focus of this McASP primer.
In this series, you will gain an understanding of the TI security framework and the various industry-recognized security enablers that TI supports.
To help explore infinite design possibilities with TI Sitara™ ARM® Processors, Texas Instruments has created the Sitara ARM Processors Boot Camp. This modular training series for TI’s Sitara ARM Processors is based on the latest development kits from TI and provides in-depth technical discussion and hands-on exercises for all aspects of the solution; from architecture to peripherals to software and development environments.
Although motor drives have been around for many years, trends in Industry 4.0 such as TSN, industrial IoT, and functional safety are revolutionizing the role a drive takes in the Smart Factory. Where typically its main function was to drive a motor, a servo drive now must include other features to conform with the needs of Industry 4.0. This paired with the rapid growth of the robotics market has created a need for Smart Servo drives with multi-axis capabilities.
Programmable Real-Time Unit and Industrial Communications Subsystem (PRU-ICSS / PRU-ICSSG) Training Series
The Programmable Real-Time Unit and Industrial Communications Subsystem (PRU-ICSS / PRU-ICSSG) is a small processor that is tightly integrated with an IO subsystem, offering low-latency control of IO pins on TI’s SoC devices including the AM335x, AM437x, AM57x, and AM65x Sitara Processors. The PRU-ICSS / PRU-ICSSG is customer-programmable and can be used to implement simple and flexible control functions, peripherals, and state machines that directly access IO pins of the device, as well as can communicate with the application cores.
TI provides key runtime software components and documentation to further ease development. TI’s online training provides an introduction to the Processor SDK and how to use this software to start building applications on TI embedded processors.
The "Linux Board Porting" online series is comprised of nine, 10-minute modules (3 Lecture and 6 Lab) that provide an introduction to porting U-boot and the Linux Kernel to custom hardware platforms.
In this training series, we demonstrate how to use the PRU-ICSS subsystem on a Sitara processor to interface between multiple SAR ADCs using SPI.
This training series looks at High Availability Seamless Redundancy (HSR) and Parallel Redundancy Protocol (PRP), which are fundamental to many of the tightly-synchronized, high-reliability systems being built today. HSR and PRP work together or separate to keep systems working even when things break so that power stays on and things keep getting built. Both of them work in the low levels of the Ethernet stack to provide the applications that they serve these fundamental capabilities.
This training presents TI’s ready-to-use EtherCAT masters solutions for Sitara processors. EtherCAT master on Sitara runs on different operating systems, including TI-RTOS and RT Linux. It also runs on the EMAC interfaces (CPSW and PRU ICSS_EMAC) of any Sitara device, including AM57x, AM437x, and AM335x.
This training series provides background on embedded systems startup to enable users of the AM3x/AM4x/AM57x Sitara processors to make choices that reduce boot time during system design of a selected processor. It introduces the boot time components of the catalog processors, system, and the Processor Linux Software Development Kit (PLSDK). It provides first steps and capabilities to reduce boot time using the Processor SDK without significant customization. This presentation also gives developers a look beyond just the initialization of the selected OS.