TI’s AM437x processors, along with the Processor SDK, deliver unrivaled integration, scalability, peripherals and ease of use associated with the powerful Sitara processor platform. The Sitara AM437xx processor architecture includes ARM® Cortex®-A9 cores, programmable real-time units (PRU), video and graphic accelerators, and customer-programmable secure boot make the AM437xx processors unmatched in their class.
The AM4x Sitara processors provide scalable ARM Cortex‐A9 solutions for automation, HMI, vision, imaging, and other industrial and high‐performance applications. This online training series includes an introduction to the AM4x processor family and the industrial .application support provided for devices in this class.
The AM57x Sitara processors provide scalable ARM Cortex‐A15 and C66x solutions for automation, HMI, vision, imaging, and other industrial and high‐performance applications. This online training series includes an introduction to the AM57x processor family, a technical deep dive into the capabilities of the SoC, and an overview of the multimedia and video capabilities.
TI’s AM6x Sitara processor family, along with the Processor SDK, brings unparalleled scalability, reliability, integration, and ease-of-use to the Sitara product line. The new, highly-integrated Sitara AM6x processor family provides industrial-grade reliability, with quad and dual Arm® Cortex®-A53 core variants built to meet the rapidly evolving needs of Industry 4.0 in factory automation and grid infrastructure.
Advanced closed-loop control systems for factory, process, and power automation markets require powerful MCU solutions that can interface to variety of industrial communications protocols. As new features and capabilities are added, these protocols may evolve several times during the lifetime of an industrial product. As a result, system providers can benefit from solutions that flexibly support multiple communications protocols and in-service updates without updating hardware.
Debugging Embedded Linux Systems training series teaches the techniques of debugging kernel issues that may be encountered in embedded Linux systems. It explains the Linux kernel logging system and logging API, illustrates how to locate a particular device driver, and demonstrates how to read kernel oops logs.
Linux is well-adopted within embedded systems. But debugging Linux system issues can be overwhelming. This training series teaches the techniques of debugging kernel issues that may be encountered in embedded Linux systems. This training series explains the Linux kernel logging system and logging API, illustrates how to locate a particular device driver, and demonstrates how to read kernel oops logs.
This training series provides background on embedded systems startup to enable users of the AM3x/AM4x/AM57x Sitara processors to make choices that reduce boot time during system design of a selected processor. It introduces the boot time components of the catalog processors, system, and the Processor Linux Software Development Kit (PLSDK). It provides first steps and capabilities to reduce boot time using the Processor SDK without significant customization. This presentation also gives developers a look beyond just the initialization of the selected OS.
This training presents TI’s ready-to-use EtherCAT masters solutions for Sitara processors. EtherCAT master on Sitara runs on different operating systems, including TI-RTOS and RT Linux. It also runs on the EMAC interfaces (CPSW and PRU ICSS_EMAC) of any Sitara device, including AM57x, AM437x, and AM335x.
This section contains task-specific videos that demonstrate how to perform debugging techniques on embedded Linux systems.
This training series looks at High Availability Seamless Redundancy (HSR) and Parallel Redundancy Protocol (PRP), which are fundamental to many of the tightly-synchronized, high-reliability systems being built today. HSR and PRP work together or separate to keep systems working even when things break so that power stays on and things keep getting built. Both of them work in the low levels of the Ethernet stack to provide the applications that they serve these fundamental capabilities.
In this training series, we demonstrate how to use the PRU-ICSS subsystem on a Sitara processor to interface between multiple SAR ADCs using SPI.