3.3 Standard Logic - CMOS Inputs

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Description

May 3, 2018

Introduction to the Standard Logic and Translation Family. A generic CMOS input structure is discussed along with it's typical characteristics and behavior. Use cases for Logic gates are discussed as well.

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1Application specific logic (3)

This series offers insight into a set of Logic use cases relevant to a particular group of systems and equipment.

04:15

1.1 Enabling Image Sensor to Process Interfaces with Level Translation

02:32

1.2 Understanding Bus Hold Functionality for Level Translators

01:57

3.3 Standard Logic - CMOS Inputs

Description

Additional information

1Application specific logic (3)

1.1 Enabling Image Sensor to Process Interfaces with Level Translation

1.2 Understanding Bus Hold Functionality for Level Translators

1.3 Voltage translation in switches and routers

2Overviews of devices and EVMs (8)

2.1 Introduction to the SN74AXC4T774

2.2 Introducing the 2N7001T level shifter

2.3 Introduction to the SN74AXC4T245 four bit low voltage direction controlled level translator

2.4 Introducing the SN74AXCH4T245 4-bit low voltage direction controlled level translator with bus hold

2.5 Discrete Level Translation Replacement

2.6 X1QFN: The industry's smallest QFN package

2.7 TIs New Space Saving Package

2.8 Introducing the SN74AXCH8T245 8-bit direction controlled level translator with bus hold

3Other logic (9)

3.1 Understanding the pitfalls of discrete level shifting circuits

3.2 Clamp Diodes

3.3 Standard Logic - CMOS Inputs

3.4 Understanding schmitt trigger

3.5 CMOS Logic Outputs

3.6 Understanding Flip-flops,shift registers

3.7 Signal Level Translation

3.8 Outputs of Clocked Devices

3.9 Solving Voltage Translation Solutions With One Power Rail

3.3 Standard Logic - CMOS Inputs

Description

Additional information

1Application specific logic (3)

2Overviews of devices and EVMs (8)

3Other logic (9)

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