Synchronization of High Speed Multichannel JESD204B Compliant Clocks Part 1
Description
July 17, 2018
Learn about the multi-channel clock requirements for high speed data acquisition systems including the JESD204B serial interface standard, clock impact on interleaved ADCs, and giga-sample multi-channel clocks challenges.
Additional information
This course is also a part of the following series
Date: July 23, 2018
Date: April 22, 2016
