TI Precision Labs - ADCs (45)
Error and Noise (5)
September 10, 2018
In this section we gain a basic understanding of a custom SAR ADC reference input SPICE model based on datasheet parameters. This particular model is called the “Discrete Charge model” and is based on the switching capacitive load of the SAR ADC at the reference input. The SPICE model can be used to verify the settling performance on the voltage reference input so that we can be confidant that ADC performance is not limited by the reference design.
1Introduction to Analog-to-Digital Converters (ADCs) (1)
These videos describe the key specifications listed in an analog-to-digital converter data sheet.
2Analog-to-Digital Converter (ADC) Drive Topologies (5)
These videos describe the different types front-end topologies that can be used to drive the input signal of an ADC.
3Error and Noise (5)
These videos describe how to calculate error and noise of analog-to-digital converters (ADCs).
4AC Specifications (5)
These videos describe how to analyze analog-to-digital converter (ADC) performance specifications that are measured using ac input signals.
5SAR ADC Input Driver Design (7)
These videos describe how to design the input driver circuitry for a successive approximation register analog-to-digital converter (SAR ADC).
6Driving the Reference Input on a SAR ADC (6)
This section covers SAR voltage reference specifications, reference behavior, and methods for driving the reference input that minimize error.
7Low-power SAR ADC System Design (2)
These videos describe how to design a low-power data acquisition system using a successive approximation register analog-to-digital converter (SAR ADC).
8Electrical Overstress on Data Converters (7)
This series covers methods for protecting a system with an ADC with external components and how to minimize the impact of protection components on performance.
9High-Speed Analog-to-Digital Converter (ADC) Fundamentals (7)
These videos cover the fundamentals of high-speed data converters, including an overview of the architectures of both ADCs and DACs.