Hello, and welcome to the Logic Minute. In this video, the sixth installment of the LSF family series, we will explain how LSF devices achieve up translation. This is a simplified schematic for up translating with an LSF device. A device powered from the A supply is transmitting into the A side of the LSF, and a device powered from the B supply is receiving the signal after translation. The transmitter is on the low side of the LSF and has a Push-Pull output, which will either be driving the A1 input of the LSF to VA or to ground. The receiver has a high impedance standard CMOS input.

Before we get into how the translation works, we need to add a few more components to this circuit. A pull-up resistor was added on both sides of the device. Each line also has a parasitic capacitance associated with it, labeled here as CA1 and CB1. This capacitance comes from the trace and attached devices. The pairs of the capacitors are shown here grayed out as a reminder that they are not real components.

We're going to break down the translation into two sections-- when the transmitter is driving the input low and when the transmitter is driving the input high. When the transmitter is driving the input low, the channel one FET of the LSF is turned all the way on and is essentially acting like a resistor. The input at the receiver is driven low, as well, through the FET.

It's important to note that in this state, current will be generated by both pull-up resistors, and that current will sink into the transmitter. The current IB passing through the FET will produce a small voltage drop, shown here is VBA, and therefore, the voltage at B1 and the input to the receiver will be slightly higher than the voltage at A1.

When the transmitter drives the line high, the output voltage will follow the input until the FET turns off, which happens at approximately VA, in this case. Once the FET turns off, the output goes into a high impedance state. The voltage at B1 will remain at approximately VA, due to the parasitic capacitance CB1, since capacitors can't change voltage instantaneously. Now that the B1 voltage node is essentially disconnected, the passive RC circuit will drive the receiver's input up to VB and hold it there.

Now we will look at a typical up translation waveform and break it down, to relate it back to the circuit we just discussed. First, note that the input voltage, shown in green here, is not quite at 0 in the low state. This is referred to as VOL and is the voltage across the driver's NFET. It is usually a very small value, but can become significant if too much current is sinking into the driver.

Because of how the LSF works, the output voltage will always be slightly higher than the input voltage in the low state. Recall that some current is flowing through the LSF and will produce a voltage increase from input to output. During the translation from low to VA, the output will closely follow the input. Since they are essentially connected by a small resistance inside the LSF, as the input approaches the threshold value of the internal FET, it'll start to turn off. Once the internal FET of the LSF significantly increases in impedance, the output voltage will become purely controlled by the passive components on the line, namely the pull-up resistor and any parasitic capacitances.

The output voltage rise time will be a function of the RC time constant and can be estimated as 2RC, which is how long it takes to get to approximately 86% additional charge from the forced voltage of VA to the final voltage of VB. In this example, the force voltage is 1.8 volts. Then the passive RC circuit pulls up the remainder of the way to 5 volts. This passive charging is why the LSF is often referred to as a passive translator. It's important to note that this RC curve doesn't show up on the falling edge, because the LSF's internal FET is turned on during this time, and the output is actively being forced low by the transmitter.

In any up translation circuit with the LSF, you have to balance two important factors. These are maximum data rate and maximum sync current. The maximum data rate is directly related to the slow-rising edge we just saw on the previous slide. A pulse that's three times the width of the rising edge is a good minimum to set, so this equation finds the bit rate for that pulse width. The maximum sync current is related to the supply values and the chosen pull up resistor values. Note that this equation is only an estimation of the final current, as it does not include the voltage dropped across the LSF device.

To clarify it, let's work a quick example. If the parasitic capacitance is estimated at 15 picofarads on each line, and the pull-up resistor values are 330 ohms and 10 kilohms, then we can calculate the maximum data rate and sync current. The maximum data rate turns out to be 33.67 megabits per second, which we can also write as 16.835 megahertz. Note that this frequency is referring to a squarewave clock specifically.

The maximum sync current is the sum of current through each pull-up resistor. And in this case, you can see that the A side resistor doesn't contribute much current, only 140 microamps. This current value is only an estimation, but the final operating current will be slightly lower. So its a good value to use for choosing a driver.

This is a typical schematic for the LSF0102 up translating from a 1.8 volt device to a 3.3 volt device, including both a push-pull output and an open drain output. It's interesting to note that this is also the circuit that would be used for a bidirectional translation. The pull-up resistors are always required on the high side, and pull-ups are only required on the low side if the low side device's output is open drain or its input has a leakage greater than 1 microamp. Please click on the links below to jump to the video of interest, and thank you for watching.