Voltage regulator design and optimization for high-current, fast-slew-rate load transients
Designing to the tight voltage tolerances of today’s modern central processing units and field programmable gate arrays (FPGAs) is becoming more difficult as their current draw increases and becomes more dynamic. Getting the correct output capacitance mix to ensure first-time power-delivery success is no small feat with >100-A steps and slew rates in excess of 100 A/µs. Standard point-of-load design techniques no longer hold true; we need new methods to choose the output capacitance.
This series breaks down regulator transient response, the effects of load slew rate on COUT selection and two methods of calculating COUT in processor power applications. The first method is a charge-based approach in the time domain, while the second method calculates a target impedance across a range of frequencies. When used in conjunction with one another, these approaches meet the transient specifications of a high-current FPGA core voltage rail. These videos also includes an overview of regulator output impedance, load lines and the effect of control topology on transient response.
Why should I take this training?
- Principles discussed are accessible and applicable to a broad base of applications
- Limitations of conventional design techniques are highlighted
- High-power processors present extreme dynamic requirements for power supplies
What will I learn?
- How load transients impact regulator design
- Output capacitor selection methods
- Influence of control schemes
- Benefits of DC load lines