Power switching device cannot drive themselves - Mastering the art of high voltage gate driver design
We live in a world where designers are constantly pursuing higher efficiencies and higher power densities. Our customers want more power out with less power loss while achieving smaller solution sizes. They strive to reduce switching losses while maintaining signal integrity. The need for higher efficiency and power density is a trend seen across isolated and non-isolated power systems in uninterruptible power supplies (UPS), telecom rectifiers, and server PSUs.
Efficiency is a team effort that includes, but is not limited to, better performing gate drivers, controllers, and power devices. High voltage switching devices have seen exponential improvements in new technologies (like SiC-MOSFETS, GaN transistors, trench/field-stop IGBTs and super-junction MOSFETs) and dynamic performance (like switch-transition speed, switching loss and body/anti-parallel reverse recovery). These improvements, however, cannot be fully realized without robust, fast and smart high voltage gate drivers. These gate drivers are necessary to handle high dv/dt, high di/dt and fast propagation delays.
This in-depth discussion will cover how to drive these state-of-the-art power transistors and key design considerations that our customers face. Topics will include:
- Parasitic influences
- Hard switching vs soft switching
- Non-linear junction capacitance (CRSS, COSS)
- Common-mode transient immunity (CMTI)
- Turn-off negative bias
- Separating power/ground noise
- Trade-offs between different isolated DC-DC topologies for powering gate drivers
We will also highlight how our reference designs and strong gate driver portfolio address design challenges found in UPS, telecom rectifiers and server PSUs. Parts discussed will include our first 600-V/700-V half-bridge gate driver, UCC2771X and the industry's fastest isolated dual-channel gate driver, UCC2152X and simple single-channel isolated IGBT/SiC gate drivers, ISO53xx.