4.2 Robust design of Delta-Sigma ADC system inputs for EOS immunity – PLC analog input module
Industrial TI Tech Days session
Electrical overstress (EOS) damage is one of the most common issues affecting product reliability. The EOS failures that occur from improperly designed circuits can damage a company’s reputation and cause revenue loss, and may even present legal issues. The overstress susceptibility issue may be detected during compliance testing, but is often only seen in the end user’s application. It’s common to blame EOS susceptibility on the device, but often, the issue can avoided with well-designed overstress protection circuitry. This presentation will show you how to design protection circuitry that will prevent damage to the delta-sigma ADC from large EOS signals with little to no impact on the circuit performance. A detailed, definition-by-example design of a delta-sigma ADC acquisition system will be presented with consideration of application usages, including RTD, TC and voltage/current measurement in analog input module (AI) of programmable logic controller (PLC) and proper selection of external protection circuitry. Design techniques will include hand calculations, TINA-TI SPICE analysis and real-world measured results including EMC testing (IEC61000-4-x). The design will consider the impact of parasitics from the protection circuitry, and their effects on system performance. For example, many protection diodes have parasitic capacitance and leakage current that can impact accuracy. The methods covered will enable you to create a first-pass, robust PCB design, so you can avoid future EOS issues.