注意:各項之間請以逗號分隔

例如 , 12/01/2021

例如 , 12/01/2021

注意:各項之間請以逗號分隔

例如 , 12/01/2021

例如 , 12/01/2021

排序方式:

105 結果

How to synchronize high speed multi-channel clocks?

This training explains how to synchronize high speed multi-channel clocks used in high-speed end equipment with multi-channel transceiver system.

Synchronization of High Speed Multichannel JESD204B Compliant Clocks Part 1

日期:
2018年 7月 17日

時間長度:
07:50
Learn about the high speed multi-channel clocking requirements and challenges.

How to Select Display SerDes for HMI Systems

日期:
2018年 5月 8日

時間長度:
04:19
How to select proper serializer and deserializer for the signal transmission in the relevant applications of human-machine interface (HMI).

Get Your Clocks in Sync for JESD204B Data Converters

日期:
2017年 9月 6日

時間長度:
19:17
This video will explore a reference design that shows how to synchronize multiple high-speed JESD204B data converters.

Get Your Clocks in Sync: Hardware Setup

日期:
2017年 8月 14日

時間長度:
02:31
This video demonstrates DEV_CLK skew between two clock outputs of the clocking reference design and the analog channel to channel skew between 2 ADC12DJ3200EVMs

Get Your Clocks in Sync: Software Setup

日期:
2017年 8月 7日

時間長度:
04:20
This video demonstrates the software setup of the Multi-Channel JESD204B 15 GHz Clocking Reference Design for DSO, Radar and 5G Wireless Testers

How to read an SMD part number

日期:
2017年 2月 7日

時間長度:
04:38
Learn how to read a SMD (Standard Microcircuit Drawing) part number.
SEPIC Mode Converters for Automotive LCD Displays Technical Overview

SEPIC Mode Converters for Automotive LCD Displays - Technical Overview

日期:
2016年 9月 22日

時間長度:
20:26
Learn the basics of a DC/DC SEPIC converter, its advantages compared to other DC/DC topologies, and how a SEPIC can help you in your Automotive display design.

Wearable displays with our DLP® Pico™ technology

This training discusses wearable display systems and design considerations.

Jump-Start Your Space Design with the TPS7H3301-SP Evaluation Module

日期:
2016年 7月 8日

時間長度:
04:58
The TPS7H3301-SP is the first double-data-rate (DDR) memory-termination LDO for space applications.

Understanding TI's Enhanced Products Value and Risk Mitigation

日期:
2016年 6月 24日

時間長度:
04:38
TI’s broad portfolio of enhanced products provide ruggedized components in plastic packaging. Learn about the qualification process and more.

ADC32RF45: 1-GHz Bandwidth RF Sampling Solution

日期:
2016年 5月 15日

時間長度:
05:04
The ADC32RF45 is a dual channel, 14-bit, 3-GSPS ADC. This video shows how the ADC32RF45 supports 1-GHz signal bandwidths and beyond for next generation systems.

Understanding Clock Jitter Impact to ADC SNR

日期:
2015年 7月 21日

時間長度:
02:57
This video discusses the sampling clock phase noise performance and how its performance over frequency offset impacts the GSPS ADC SNR performance.

High-speed signal chain training series

Your portal to relevant training material on high-speed data converters and high-speed amplifiers.

Selecting a JESD204B Subclass

日期:
2015年 7月 15日

時間長度:
05:14
This video discusses the three subclass modes in the JESD204B standard.  The pros and cons of operating in each subclass is discussed.

Introduction to the RF Sampling Architecture

日期:
2015年 6月 29日

時間長度:
03:21
Introduction to the RF sampling architecture in contrast to traditional direct conversion architectures typically used in existing transceivers.

Why RF Sampling

日期:
2015年 6月 29日

時間長度:
03:15
This video specifically addresses the benefits and advantages RF sampling provides that was limited or not possible with existing technology.

RF Sampling: Managing Data Rates

日期:
2015年 6月 29日

時間長度:
03:40
RF Sampling requires fast sampling rates, but the input data rates usually cannot keep pace.  The techniques to mitigate those limitations are addressed.

Synchronizing Multiple JESD204B ADCs

日期:
2015年 6月 11日

時間長度:
03:04
This video illustrates synchronizing two ADC12J4000 ADCs employing JESD204B interface
105 結果
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