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例如 , 09/26/2021

例如 , 09/26/2021

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103 結果

DS90UR905/906 FPD-Link II Automotive Display SerDes

日期:
2014年 11月 2日

時間長度:
29:36
Introduction to TI's DS90UR905/906 FPD-Link II automotive-qualified display interface SerDes for 24-bit color depth, higher resolution displays.

Channel Link II & III SerDes for Imaging & Displays

日期:
2014年 11月 2日

時間長度:
05:32
TI's new Channel Link Ser/Des families combine high-speed video, clock, and bi-directional control signals over a single twisted wire pair.

How to sample and decimate RF frequencies with ADC12J4000

日期:
2014年 11月 4日

時間長度:
05:33
Engineers Ken Chan and Ebenezer Dwobeng demonstrate the capabilities of TI's giga-sampling ADC. They use the ADC12J4000 to sample an input signal of 2.14GHz at

LMK03806超低抖动时钟发生器与SAW解决方案的对比

日期:
2014年 12月 13日

時間長度:
05:51
介绍简单易用和低材料成本的LMK03806超低抖动时钟发生器,并且即场证实其抖动与SAW振荡器解决方案比较低。LMK03806 可产生极低抖动的时钟(2.27MHz至2.6 GH),而且具备14个可编程输出。

How to Optimize Synthetic Aperture Radar (SAR) Design with TI's 66AK2L06 SoC

日期:
2015年 6月 8日

時間長度:
04:39
Optimize Synthetic Aperture Radar, or SAR, with TI’s integrated 66AK2L06 system-on-a-chip. The FPGA alternative is a KeyStone-based device with a JESD204B inte

Synchronizing Multiple JESD204B ADCs

日期:
2015年 6月 11日

時間長度:
03:04
This video illustrates synchronizing two ADC12J4000 ADCs employing JESD204B interface

Introduction to the RF Sampling Architecture

日期:
2015年 6月 29日

時間長度:
03:21
Introduction to the RF sampling architecture in contrast to traditional direct conversion architectures typically used in existing transceivers.

Why RF Sampling

日期:
2015年 6月 29日

時間長度:
03:15
This video specifically addresses the benefits and advantages RF sampling provides that was limited or not possible with existing technology.

RF Sampling: Managing Data Rates

日期:
2015年 6月 29日

時間長度:
03:40
RF Sampling requires fast sampling rates, but the input data rates usually cannot keep pace.  The techniques to mitigate those limitations are addressed.

Selecting a JESD204B Subclass

日期:
2015年 7月 15日

時間長度:
05:14
This video discusses the three subclass modes in the JESD204B standard.  The pros and cons of operating in each subclass is discussed.

High-speed signal chain training series

Your portal to relevant training material on high-speed data converters and high-speed amplifiers.

Understanding Clock Jitter Impact to ADC SNR

日期:
2015年 7月 21日

時間長度:
02:57
This video discusses the sampling clock phase noise performance and how its performance over frequency offset impacts the GSPS ADC SNR performance.

ADC32RF45: 1-GHz Bandwidth RF Sampling Solution

日期:
2016年 5月 15日

時間長度:
05:04
The ADC32RF45 is a dual channel, 14-bit, 3-GSPS ADC. This video shows how the ADC32RF45 supports 1-GHz signal bandwidths and beyond for next generation systems.

Jump-Start Your Space Design with the TPS7H3301-SP Evaluation Module

日期:
2016年 7月 8日

時間長度:
04:58
The TPS7H3301-SP is the first double-data-rate (DDR) memory-termination LDO for space applications.

Wearable displays with our DLP® Pico™ technology

This training discusses wearable display systems and design considerations.
SEPIC Mode Converters for Automotive LCD Displays Technical Overview

SEPIC Mode Converters for Automotive LCD Displays - Technical Overview

日期:
2016年 9月 22日

時間長度:
20:26
Learn the basics of a DC/DC SEPIC converter, its advantages compared to other DC/DC topologies, and how a SEPIC can help you in your Automotive display design.

How to read an SMD part number

日期:
2017年 2月 7日

時間長度:
04:38
Learn how to read a SMD (Standard Microcircuit Drawing) part number.

Get Your Clocks in Sync: Software Setup

日期:
2017年 8月 7日

時間長度:
04:20
This video demonstrates the software setup of the Multi-Channel JESD204B 15 GHz Clocking Reference Design for DSO, Radar and 5G Wireless Testers

Get Your Clocks in Sync: Hardware Setup

日期:
2017年 8月 14日

時間長度:
02:31
This video demonstrates DEV_CLK skew between two clock outputs of the clocking reference design and the analog channel to channel skew between 2 ADC12DJ3200EVMs
103 結果
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