注意:各項之間請以逗號分隔

例如 , 10/16/2021

例如 , 10/16/2021

注意:各項之間請以逗號分隔

例如 , 10/16/2021

例如 , 10/16/2021

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321 結果

JESD204B for space ADC

日期:
2021年 7月 8日

時間長度:
02:10
Demo of the JESD204B in space ADC and FPGA, using the Alpha Data Xilinx XQRKU060 development kit with TI ADC12DJ3200

Extending JESD204B Link on Low Cost Substrates

日期:
2015年 6月 29日

時間長度:
03:34
This video discusses the JESD204B SERDES standard related to minimum integrity to maintain proper eye diagram. 

Introduction to the RF Sampling Architecture

日期:
2015年 6月 29日

時間長度:
03:21
Introduction to the RF sampling architecture in contrast to traditional direct conversion architectures typically used in existing transceivers.

Why RF Sampling

日期:
2015年 6月 29日

時間長度:
03:15
This video specifically addresses the benefits and advantages RF sampling provides that was limited or not possible with existing technology.

RF Sampling: Managing Data Rates

日期:
2015年 6月 29日

時間長度:
03:40
RF Sampling requires fast sampling rates, but the input data rates usually cannot keep pace.  The techniques to mitigate those limitations are addressed.

SAR and Delta-Sigma ADC Fundamentals

日期:
2015年 7月 9日

時間長度:
02:35
A comparison between two of the most common precision analog-to-digital converter (ADC) architectures: successive approximation register and delta-sigma

Understanding Clock Jitter Impact to ADC SNR

日期:
2015年 7月 21日

時間長度:
02:57
This video discusses the sampling clock phase noise performance and how its performance over frequency offset impacts the GSPS ADC SNR performance.

JESD204B Physical Layer

日期:
2015年 8月 6日

時間長度:
06:39
This video describes the JESD204B physical layer and the impact on channel integrity.  Mitigation techniques utilizing pre-emphasis and de-emphasis are illustra

JESD204B: Transport Layer

日期:
2015年 8月 6日

時間長度:
04:12
This video addresses the transport layer of JESD204B standard specifically breaking down how the data converters digital data is mapped into the SerDes frames.

SAR ADCs vs. Delta-Sigma ADCs: Different architectures for different application needs

日期:
2015年 10月 13日

時間長度:
27:54
Are you choosing between ADC architectures for current or upcoming projects? Check out this webinar, aimed at helping you decide on the best product for your ne

Engineer It- How to get data sheet values from your SAR ADC

日期:
2015年 10月 23日

時間長度:
08:47
Learn how to pick the right fully differential amplifier to get data sheet values from your high-precision SAR ADC.

Engineer It- How to select a precision DAC

日期:
2015年 10月 23日

時間長度:
08:11
Learn how to select a precision digital-to-analog converter (DAC). This video explains which specifications are the most important, including offset error, zero

Engineer It: What is ADC PSR?

日期:
2015年 10月 30日

時間長度:
17:05
In this training video, TI's Xavier Ramus demonstrates how to measure the ADC Power Supply Rejection.

Engineer It: Why Not A DC/DC Converter?

日期:
2015年 11月 2日

時間長度:
14:40
In this training video, TI's Xavier Ramus discusses the importance of not using DC/DC converters to power High-Performance analog to digital converters. 
Choosing the Best ADC Architecture for Your Application

Choosing the Best ADC Architecture: Part 1 - Introduction & Overview

日期:
2016年 1月 18日

時間長度:
07:12
This video provides an overview of some of the most popular ADC architectures in use today and highlights the advantages of each for different applications.

Choosing the Best ADC Architecture: Part 2 – The successive approximation register ADC

日期:
2016年 1月 27日

時間長度:
05:56
This video provides an overview of how a SAR ADC works. SAR ADCs provide a good trade-off between speed, resolution and power. This video walks through the typi

Choosing the Best ADC Architecture: Part 3 – The Delta-Sigma Digital Modulator

日期:
2016年 1月 27日

時間長度:
08:15
This video provides an overview of how delta-sigma ADCs work. The video discusses the typical topology, oversampling, delta-sigma modulators, and more.

Choosing the Best ADC Architecture: Part 4 – The Delta-Sigma Digital Filter

日期:
2016年 1月 27日

時間長度:
08:14
This video discusses the delta-sigma digital filter. A typical topology of a delta-sigma converter generally consists of two blocks: a delta-sigma modulator and

TI's Precision SAR ADCs in Wearable Devices

日期:
2016年 2月 5日

時間長度:
02:41
This video provides information and resources to show how TI's precision SAR ADCs are well suited for use in wearable devices.

multiSPI™ Digital Interface Overview

日期:
2016年 2月 8日

時間長度:
04:29
This video provides a quick overview of TI’s multiSPI™ digital interface. The multiSPI™ digital interface is a digital interface that’s included on precision SA
321 結果
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