注意:各項之間請以逗號分隔

例如 , 09/18/2021

例如 , 09/18/2021

注意:各項之間請以逗號分隔

例如 , 09/18/2021

例如 , 09/18/2021

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333 結果
ADC drive topologies: using an INA

Determining a SAR ADC’s Linear Range when using Instrumentation Amplifiers

日期:
2017年 4月 14日

時間長度:
09:17
This video shows how to design a front-end instrumentation amplifier drive circuit for linear operation.
4-20mA input

Designing a Multi-Channel 4-20mA Analog Input Module

日期:
2017年 6月 21日

時間長度:
37:30
This training discusses real-world system requirements for a multi-channel 4-20mA analog input module for programmable logic controller (PLC).

Introduction to Frequency Domain

日期:
2017年 4月 14日

時間長度:
11:18
This video introduces the concept of the frequency domain.
Fast Fourier Transforms (FFT)

Fast Fourier Transforms (FFTs) and Windowing

日期:
2017年 4月 14日

時間長度:
10:46
This video introduces the FFT as well as the concept of windowing to minimize error sources.
Coherent Sampling

Coherent Sampling and Filtering to Improve SNR and THD

日期:
2017年 4月 14日

時間長度:
06:59
This video introduces the concept of coherent sampling and filtering for accurate characterization.

Building the SAR ADC Model

日期:
2017年 4月 14日

時間長度:
12:17
This video walks through the process of creating a TINA Spice Model for a SAR ADC.

Refine the Rfilt and Cfilt Values on ADC Drive

日期:
2017年 4月 14日

時間長度:
13:43
This video walks through the process for optimizing the selection of the external R and C values.

Final SAR ADC Drive Simulations

日期:
2017年 4月 14日

時間長度:
06:36
This video shows the simulation results using the external R and C components from the previous videos.

Math Behind the R-C Component Selection

日期:
2017年 4月 14日

時間長度:
06:10
This video walks through the mathematical algorithm used in the ADC SAR Drive Calculator.

Selecting and Verifying the Driver Amplifier

日期:
2017年 4月 14日

時間長度:
09:02
This video walks through the process of selecting the driver amplifier and verifying its SPICE model.

Using SPICE Monte Carlo Tool for Statistical Error Analysis

日期:
2017年 4月 14日

時間長度:
07:09
This video shows how the TINA-SPICE Monte Carlo analysis can be used for statistical error analysis.

Understanding and Calibrating the Offset and Gain for ADC Systems

日期:
2017年 4月 14日

時間長度:
13:22
This video discusses how gain and offset errors can be calculated and eliminated through calibration.
Alias and Anti-Alias Filters

Aliasing and Anti-aliasing Filters

日期:
2017年 4月 14日

時間長度:
13:19
This video introduces the concept of frequency domain aliasing and why anti-aliasing filters are needed.

Precision Signal Injector Demo

日期:
2017年 6月 23日

時間長度:
01:01
High Precision Digital to Analog Converter Training with Signal High-Fidelity Source Evaluation Module showcases our most precise data converter, the ADS8900B.
Understanding Sampling Rate vs Data Rate, Decimation (DDC) and Interpolation (DUC) Concepts in High Speed Data Converters

Understanding signal to noise ratio and noise spectral density in high speed data converters

日期:
2017年 7月 28日

時間長度:
14:32
Concepts of Signal to Noise Ratio and Noise Spectral Density; an example on how NSD is used to estimate the DAC output as it pertains to noise floor.

Comparing high-speed analog-to-digital (ADC) and digital-to-analog (DAC) converter architectures

日期:
2017年 8月 2日

時間長度:
18:40
Overview of high-speed data converter architectures: pipeline, interleaved, Successive Approximation Register (SAR), DAC current source and current sink.
Bandwidth vs Frequency(Subsampling Concepts)

Bandwidth vs. Frequency - Subsampling Concepts

日期:
2017年 7月 31日

時間長度:
09:17
Learn more about subsampling concepts pertaining to bandwidth vs. frequency, including: Nyquist frequency, aliasing, under-sampling, and input bandwidth.
Understanding Sampling Rate vs Data Rate, Decimation (DDC) and Interpolation (DUC) Concepts in High Speed Data Converters

Sampling vs. data rate, decimation (DDC) and interpolation (DUC) in high-speed data converters

日期:
2017年 7月 31日

時間長度:
18:41
Explore the differences between sample rate and data rate and use decimation or interpolation to decrease or increase the data rate.
Jitter vs SNR for High Speed ADCs

Jitter's impact on signal-to-noise ratio (SNR) for high-speed analog-to-digital converters (ADCs)

日期:
2017年 7月 31日

時間長度:
08:00
Considerations of Clock jitter, the impact on SNR, how to calculate it and minimize noise degradation for High-Speed Analog-to-Digital Converters.

Get Your Clocks in Sync: Hardware Setup

日期:
2017年 8月 14日

時間長度:
02:31
This video demonstrates DEV_CLK skew between two clock outputs of the clocking reference design and the analog channel to channel skew between 2 ADC12DJ3200EVMs
333 結果
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