注意:各項之間請以逗號分隔

例如 , 09/19/2020

例如 , 09/19/2020

注意:各項之間請以逗號分隔

例如 , 09/19/2020

例如 , 09/19/2020

排序方式:

14 結果

Reduce design risk for Low Earth Orbit satellites and other New Space applications

時間: 2019年 10月 8日 14:00
What is NewSpace? What does it mean for satellite design? Explore products that meet quality & reliability requirements for short space flights and LEO designs.

Clocking Solutions for High Speed Multi-Channel Applications

Explore clocking solutions for a variety of high speed multi-channel applications. 

LVDS Training Series

LVDS Fundamentals

New to LVDS technology? Start with the LVDS fundamentals. 
M-LVDS backplanes

M-LVDS in Backplanes

Providing discussion on topics related to using M-LVDS in backplane applications supporting data rates up to 250 Mbps and are IEC 61000-4-2 compliant.

Webinar - What you need to know about Clock Generators, Buffers and RF Synthesizers

日期:
2018年 6月 27日

時間長度:
54:18
Want to learn more about Clock Generators and Buffers ? You're in the right place!
Fanout Universal Clock Buffers

Engineer It: How to measure additive jitter in fanout buffers

日期:
2016年 4月 19日

時間長度:
12:07
Learn how to properly measure residual noise of clock fanout buffers

Selection of Key Components (ADC, Signal Conditioning Amplifier) for AC Analog Input Module (AIM)

日期:
2017年 4月 15日

時間長度:
12:30
Understand some of the key criteria for selection of ADC, Signal Conditioning Amplifier and TI focus products for AC Analog Input Module.

LVDS Overview

日期:
2018年 4月 19日

時間長度:
05:49
This video provides an overview of LVDS technology, explains its operation, and clarifies the difference between LVDS and other interfaces.

Advantages of LVDS

日期:
2018年 4月 23日

時間長度:
06:35
Deep dive into the advantages of LVDS such as data rate, low power consumption, noise immunity, and EMI reduction for point to point communication interface.
LVDS Series

LVDS Training Series

The LVDS training series is designed for learning the fundamentals of Low Voltage Differential Signalling technology. It begins with an overview of LVDS technology, and then expands on the advantages of using LVDS such as noise immunity, EMI reduction, low power, and etc. Next, M-LVDS and communication typologies commonly used with LVDS/M-LVDS Interface are explained. Typical use case of LVDS interface and how to calculate LVDS data rate are presented in this training series as well. 

TI Precision Labs - Clocks and Timing: System Design Considerations

The videos in this series will discuss distributed vs. centralized clock tree, synchronous vs. free-running designs and other selection criteria requirements to help narrow down a clock tree solution. We will discuss other design considerations including frequency planning, spurious and EMI noise reduction techniques, system clock optimization/tuning and clocking for JESD204 B/C systems.

Engineer It : 如何测量附加抖动扇出缓冲器

日期:
2016年 5月 5日

時間長度:
12:07
了解如何正确测量残余噪声的时钟扇出缓冲器,这样就不会影响到会降低高精度应用中的系统性能从 Jim Catt, 是 TI 时钟应用小组的经理。

LMK0033x: Industrys lowest jitter PCIe buffers

日期:
2014年 11月 8日

時間長度:
04:28
Alan demonstrates the performance of the LMK00338 HCSL fanout buffer in combination with the CDCM6208

WEBENCH® Clock Architect: A success story

日期:
2014年 11月 4日

時間長度:
02:32
Alan and Jeramie show you how to build a complete, optimized clock tree in minutes with WEBENCH® Clock Architect
14 結果
arrow-topclosedeletedownloadmenusearchsortingArrowszoom-inzoom-out arrow-downarrow-uparrowCircle-leftarrowCircle-rightblockDiagramcalculatorcalendarchatBubble-doublechatBubble-personchatBubble-singlecheckmark-circlechevron-downchevron-leftchevron-rightchevron-upchipclipboardclose-circlecrossReferencedashdocument-genericdocument-pdfAcrobatdocument-webevaluationModuleglobehistoryClockinfo-circlelistlockmailmyTIonlineDataSheetpersonphonequestion-circlereferenceDesignshoppingCartstartoolsvideoswarningwiki