注意:各項之間請以逗號分隔

例如 , 12/16/2019

例如 , 12/16/2019

注意:各項之間請以逗號分隔

例如 , 12/16/2019

例如 , 12/16/2019

排序方式:

11 結果

Get Your Clocks in Sync: Hardware Setup

日期:
2017年 8月 14日

時間長度:
02:31
This video demonstrates DEV_CLK skew between two clock outputs of the clocking reference design and the analog channel to channel skew between 2 ADC12DJ3200EVMs

Get Your Clocks in Sync: Software Setup

日期:
2017年 8月 7日

時間長度:
04:20
This video demonstrates the software setup of the Multi-Channel JESD204B 15 GHz Clocking Reference Design for DSO, Radar and 5G Wireless Testers

TI Solutions for Clock and Timing

日期:
2017年 12月 7日

時間長度:
15:08
Learn about solutions to common aerospace and defense design challenges to help you simplify designs and improve performance.

Reduce design risk for Low Earth Orbit satellites and other New Space applications

時間: 2019年 10月 8日 14:00
What is NewSpace? What does it mean for satellite design? Explore products that meet quality & reliability requirements for short space flights and LEO designs.

How to synchronize high speed multi-channel clocks?

Modern high speed end equipment's like oscilloscope, 5G wireless communication tester and RADAR requires multichannel transceiver system. The biggest challenge is to provide the high frequency, low phase noise, multiple synchronized clocks to each transceiver's data converters and local oscillator. This training will explain how to synchronize the high speed multi-channel clocks and expand for high channel count clocks requirement.

TX Signal Chain Implementation for Wide Band and High Frequency Signal Generation

日期:
2016年 11月 10日

時間長度:
13:45
The system design for an arbitrary waveform generator (AWG) and its functional blocks, including a discussion of the AWG amplifier path and design methodology.

Design Considerations for Robust Interface Between J6 and Car Displays via FPD-Link [Part 3]

日期:
2017年 4月 21日

時間長度:
03:14
Clock cleaners can be incorporated into a system design if jitter issues continue after PCB guidelines and followed and PLL configurations are optimized.

Get Your Clocks in Sync for JESD204B Data Converters

日期:
2017年 9月 6日

時間長度:
19:17
This video will explore a reference design that shows how to synchronize multiple high-speed JESD204B data converters.

Synchronization of High Speed Multichannel JESD204B Compliant Clocks Part 1

日期:
2018年 7月 17日

時間長度:
07:50
Learn about the high speed multi-channel clocking requirements and challenges.

Synchronization of High Speed Multichannel JESD204B Compliant Clocks Part 2

日期:
2018年 7月 25日

時間長度:
09:56
Learn about the JESD204B compliant high speed multichannel synchronized clocking architecture

Synchronization of High Speed Multichannel JESD204B Compliant Clocks Part 3

日期:
2018年 7月 25日

時間長度:
11:22
Learn about the high channel count clocking solution.
11 結果
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