注意:各項之間請以逗號分隔

例如 , 09/19/2020

例如 , 09/19/2020

注意:各項之間請以逗號分隔

例如 , 09/19/2020

例如 , 09/19/2020

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32 結果

Reduce design risk for Low Earth Orbit satellites and other New Space applications

時間: 2019年 10月 8日 14:00
What is NewSpace? What does it mean for satellite design? Explore products that meet quality & reliability requirements for short space flights and LEO designs.

Clocking Solutions for High Speed Multi-Channel Applications

Explore clocking solutions for a variety of high speed multi-channel applications. 

Program Clock Distribution Circuits - ClockPro

日期:
2014年 11月 8日

時間長度:
01:47
Learn how to program TIClock Pro and TI Clock distribution circuits using ClockPro software.

Frequency planning and loop filter design using CDCE62005

日期:
2014年 11月 1日

時間長度:
04:14
Planning and loop filter design is now easy using the latest tools available in the CDCE62005 GUI.

Optimize System Performance and Design Time with the LMK03328 Ultra-Low-Jitter Clock Generator

日期:
2015年 9月 28日

時間長度:
07:12
Deepa shows us how easy it is to implement the LMK03328 features in your system design.

システム性能の最適化と設計時間 超低クロック・ジェネレータ LMK03328

日期:
2016年 1月 13日

時間長度:
07:12
今日はTIの最新クロック・ジェネレータLMK03328の性能および機能に関するデモをお見せします。

Hitless Switching with DPLL Network Clock Synchronizers from TI

日期:
2018年 3月 27日

時間長度:
01:18
Hitless Switching: Watch how our innovative phase cancellation eliminates phase hits in clock applications.

Better Clocking for Serial Link Applications: TI's BAW-Based LMK05318

日期:
2018年 12月 11日

時間長度:
04:27
This video provides an overview of TI's BAW-based network synchronizer clock device and its benefits in clocking 400G serial link applications.

TI's Bulk Acoustic Wave Clocking Technology

日期:
2019年 2月 22日

時間長度:
03:02
This video details TI’s Bulk Acoustic Wave (BAW) clocking technology, optimized to improve network performance, reduce BOM and increase immunity to interference

Synchronization of High Speed Multichannel JESD204B Compliant Clocks Part 1

日期:
2018年 7月 17日

時間長度:
07:50
Learn about the high speed multi-channel clocking requirements and challenges.

TX Signal Chain Implementation for Wide Band and High Frequency Signal Generation

日期:
2016年 11月 10日

時間長度:
13:45
The system design for an arbitrary waveform generator (AWG) and its functional blocks, including a discussion of the AWG amplifier path and design methodology.

Design Considerations for Robust Interface Between J6 and Car Displays via FPD-Link [Part 3]

日期:
2017年 4月 21日

時間長度:
03:14
Clock cleaners can be incorporated into a system design if jitter issues continue after PCB guidelines and followed and PLL configurations are optimized.

TI Precision Labs - Clocks and Timing: Clocking JESD204B/C Systems

日期:
2020年 6月 30日

時間長度:
10:07
Clocking JESD204B or JESD204C systems.
LMK03328 Frequency Margining

LMK03328 Frequency Margining and EEPROM programming with TICS Pro GUI

日期:
2017年 1月 13日

時間長度:
04:41
LMK03328 frequency margining example for generating multiple frequency plan configurations (nominal, margin high, and margin low) and programming these to the E
LMK03328EVM setup

LMK03328 EVM Setup and Programming with TICS Pro GUI

日期:
2017年 1月 13日

時間長度:
08:50
EVM setup and programming using TICS Pro GUI with WEBENCH clock design report to configure and program the device.  The video also covers frequency planning tec

Get Your Clocks in Sync for JESD204B Data Converters

日期:
2017年 9月 6日

時間長度:
19:17
This video will explore a reference design that shows how to synchronize multiple high-speed JESD204B data converters.

Get Your Clocks in Sync: Hardware Setup

日期:
2017年 8月 14日

時間長度:
02:31
This video demonstrates DEV_CLK skew between two clock outputs of the clocking reference design and the analog channel to channel skew between 2 ADC12DJ3200EVMs

Get Your Clocks in Sync: Software Setup

日期:
2017年 8月 7日

時間長度:
04:20
This video demonstrates the software setup of the Multi-Channel JESD204B 15 GHz Clocking Reference Design for DSO, Radar and 5G Wireless Testers

TI Solutions for Clock and Timing

日期:
2017年 12月 7日

時間長度:
15:08
Learn about solutions to common aerospace and defense design challenges to help you simplify designs and improve performance.

How to synchronize high speed multi-channel clocks?

Modern high speed end equipment's like oscilloscope, 5G wireless communication tester and RADAR requires multichannel transceiver system. The biggest challenge is to provide the high frequency, low phase noise, multiple synchronized clocks to each transceiver's data converters and local oscillator. This training will explain how to synchronize the high speed multi-channel clocks and expand for high channel count clocks requirement.
32 結果
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