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例如 , 09/27/2021

例如 , 09/27/2021

注意:各項之間請以逗號分隔

例如 , 09/27/2021

例如 , 09/27/2021

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499 結果

Introduction to i2c: advanced topics

日期:
2020年 6月 12日

時間長度:
25:42
This presentation covers I2C clock stretching, bus arbitration, logic level translation, and selection of pull-up resistors on an I2C system.

SPI Communication Basics (modes)

日期:
2020年 6月 12日

時間長度:
15:50
This video introduces digital communication then focuses on the fundamentals of Serial Peripheral Interface (SPI).

SPI Communications Timing

日期:
2020年 6月 12日

時間長度:
11:32
This video convers SPI timing requirements such as setup, hold, and delay time.

Choosing SAR or Delta-Sigma

日期:
2017年 4月 14日

時間長度:
11:08
This video covers a step-by-step decision tree to help find the best converter for your application.

Introduction to reference noise in ADC systems

日期:
2021年 1月 26日

時間長度:
15:37
This video covers the impact that voltage reference noise has on overall ADC converter system performance, and focuses in on how input signal effects the refere

What is a smart DAC?

日期:
2021年 5月 5日

時間長度:
03:06
Smart DACs – add basic controllability to analog design without software
What is a smart AFE?

What is a smart AFE?

日期:
2021年 5月 5日

時間長度:
01:21
Smart AFEs – Add closed-loop controllability to Analog design without Software
Smart AFE TEC Control

Smart AFE for TEC control

日期:
2021年 5月 5日

時間長度:
02:22
Smart AFEs are a great closed loop solution for TEC.

Simple logic for analog with smart DACs and AFEs

日期:
2021年 5月 17日

時間長度:
01:13
Smart DACs and AFEs – Add basic controllability to Analog design without Software
Increasing signal detection with SAR ADCs

Increasing signal detection capability in industrial applications

日期:
2021年 5月 18日

時間長度:
01:58
See how to increase signal detection capability in industrial applications, with the new ADC3660 family of SAR ADCs.

Reference noise affect on signal chain performance

日期:
2021年 1月 26日

時間長度:
17:55
Describes how a system’s voltage reference interacts with amplifier and PGA gain to determine the overall system performance.

JESD204B for space ADC

日期:
2021年 7月 8日

時間長度:
02:10
Demo of the JESD204B in space ADC and FPGA, using the Alpha Data Xilinx XQRKU060 development kit with TI ADC12DJ3200

Download the webinar slides: How to design an analog front end for in-vitro diagnostic applications

日期:
2021年 7月 13日
Download the webinar slides - How to design an analog front end for in-vitro diagnostic applications (Texas Instruments)

Reducing reference noise ADC systems: ratiometric, internal, external

日期:
2021年 1月 26日

時間長度:
11:33
This video covers the noise and drift implications of using a ratiometric reference configuration, vs internal and external.

Why Use a JESD204B Device?

日期:
2015年 6月 11日

時間長度:
03:26
This video introduces the advantages that the JESD204B standard provides in high speed data converters

Synchronizing Multiple JESD204B ADCs

日期:
2015年 6月 11日

時間長度:
03:04
This video illustrates synchronizing two ADC12J4000 ADCs employing JESD204B interface

Extending JESD204B Link on Low Cost Substrates

日期:
2015年 6月 29日

時間長度:
03:34
This video discusses the JESD204B SERDES standard related to minimum integrity to maintain proper eye diagram. 

Introduction to the RF Sampling Architecture

日期:
2015年 6月 29日

時間長度:
03:21
Introduction to the RF sampling architecture in contrast to traditional direct conversion architectures typically used in existing transceivers.

Why RF Sampling

日期:
2015年 6月 29日

時間長度:
03:15
This video specifically addresses the benefits and advantages RF sampling provides that was limited or not possible with existing technology.

RF Sampling: Managing Data Rates

日期:
2015年 6月 29日

時間長度:
03:40
RF Sampling requires fast sampling rates, but the input data rates usually cannot keep pace.  The techniques to mitigate those limitations are addressed.
499 結果
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