This video illustrates synchronizing two ADC12J4000 ADCs employing JESD204B interface

This video discusses the JESD204B SERDES standard related to minimum integrity to maintain proper eye diagram. 

Introduction to the RF sampling architecture in contrast to traditional direct conversion architectures typically used in existing transceivers.

This video specifically addresses the benefits and advantages RF sampling provides that was limited or not possible with existing technology.

RF Sampling requires fast sampling rates, but the input data rates usually cannot keep pace.  The techniques to mitigate those limitations are addressed.

針對 Delta Sigma ADC 的基本作動原理做介紹, 能夠幫助使用者在實務上更能掌握情況, 遇到問題時能夠加速除錯與問題判斷. 最後介紹常見的壓力和溫度信號量測與建議做法。

 深入了解如何最佳化您的資料擷取系統，達到低雜訊及低失真的高效能。

 深入了解如何最佳化您的資料擷取系統，達到低雜訊及低失真的高效能。

 深入了解如何最佳化您的資料擷取系統，達到低雜訊及低失真的高效能。

深入了解如何最佳化您的資料擷取系統，達到低雜訊及低失真的高效能。

針對 Delta Sigma ADC 的基本作動原理做介紹, 能夠幫助使用者在實務上更能掌握情況, 遇到問題時能夠加速除錯與問題判斷. 最後介紹常見的壓力和溫度信號量測與建議做法。

A comparison between two of the most common precision analog-to-digital converter (ADC) architectures: successive approximation register and delta-sigma

This video discusses the three subclass modes in the JESD204B standard.  The pros and cons of operating in each subclass is discussed.

This video illustrates the block diagram of the JESD204B SERDES transceiver.  The function of the individual blocks is described.

This video discusses the sampling clock phase noise performance and how its performance over frequency offset impacts the GSPS ADC SNR performance.

This video describes the JESD204B physical layer and the impact on channel integrity.  Mitigation techniques utilizing pre-emphasis and de-emphasis are illustra

This video addresses the transport layer of JESD204B standard specifically breaking down how the data converters digital data is mapped into the SerDes frames.

JESD204B is a common standard for implementing a SerDes interconnection between FPGA/Processor and the data converter. 

我們針對DAC使用時客戶常見的問題, 整理10個有用的小秘訣, 無論是用在解決問題或是提升知識上, 都多少有一點兒幫助喔!