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注意:各項之間請以逗號分隔

例如 , 12/04/2021

例如 , 12/04/2021

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79 結果
Understanding Bus Hold Functionality for Level Translators

Understanding Bus Hold Functionality for Level Translators

日期:
2018年 9月 8日

時間長度:
02:32
This video provides an overview of the bus hold functionality found on many level translators and its suitability for use within applications.
What a logic part is based on its part name. What a part name means

Anatomy of a logic part number

日期:
2018年 8月 22日

時間長度:
01:27
Logic part numbers use a formulaic naming system to denote the device's functionality and features. This video reviews the components to a logic part's name.
Examples of systems that might need a power on reset signal.

Generate a Reset Signal at System Power On

日期:
2018年 6月 29日

時間長度:
01:13
How to generate a power on reset signal.
Schematic representation of matching inverted clock inputs with an inverter.

Synchronize Inverted Clock Inputs

日期:
2018年 6月 29日

時間長度:
01:04
How to synchronize devices with inverted clock inputs operating off the same clock source.

Logic and voltage translation

A list of all videos on training.ti.com related to logic and voltage translators that are not produced under the The Logic Minute.
Automotive Current Shunt Monitoring

Automotive Current Monitoring Using High Speed Amplifiers

日期:
2018年 5月 24日

時間長度:
05:11
Automotive Current Monitoring Using High Speed Amplifiers

Discrete Level Translation Replacement

日期:
2018年 5月 23日

時間長度:
00:33
Watch this EVM for 2N70001T, which is a single channel unidirectional level translation intended for Replacement of discreet channel FET.
Pitfalls of Discrete Push-Pull Level Shifting

Understanding the pitfalls of discrete level shifting circuits

日期:
2018年 5月 21日

時間長度:
08:23
This video outlines common drawbacks to discrete push-pull level shifting implementations, introducing the 2N7001T device as a discrete replacement.
2N7001T Unidirectional Level Shifter

Introducing the 2N7001T level shifter

日期:
2018年 5月 21日

時間長度:
04:59
This video introduces the 2N7001T a 1-bit unidirectional level shifter device that can be used in place of discrete push-pull level shifting implementations.

Signal Level Translation

日期:
2018年 5月 3日

時間長度:
02:03
Level translation for standard Interfaces

Understanding Flip-flops,shift registers

日期:
2018年 5月 3日

時間長度:
05:07
Understanding Shift Registers and Flip-flops

Understanding schmitt trigger

日期:
2018年 5月 3日

時間長度:
05:24
Understanding Schmitt trigger

CMOS Logic Outputs

日期:
2018年 5月 3日

時間長度:
07:21
Understanding CMOS outputs

Standard Logic - CMOS Inputs

日期:
2018年 5月 3日

時間長度:
12:40
Introduction to the Standard Logic and Translation Family. Includes generic CMOS input structure and use cases
Some signals need to be held while the system controller is off.

Hold a Signal During Controller Reset

日期:
2018年 3月 28日

時間長度:
01:56
How to use logic to hold a signal line high or low while the system controller is powered off or held in reset.
Systems can have multiple error flags that need to be monitored.

Use Fewer Inputs to Monitor Error Signals

日期:
2018年 3月 28日

時間長度:
01:59
How to use logic gates to reduce the number of inputs required to monitor multiple error flags.
Slow or noisy inputs can cause erroneous outputs.

Eliminate Slow or Noisy Input Signals

日期:
2018年 3月 28日

時間長度:
02:02
How to eliminate slow or noisy input signals.

Low Voltage Translation using SN74AXC8T245

日期:
2018年 2月 21日

時間長度:
04:09
This video introduces the industry's low voltage translator, SN74AXC8T245 along with an application to demonstrate the translation using the SN74AXC8T245EVM
Example signal enable circuits.

Enable or Disable a Digital Signal

日期:
2017年 11月 16日

時間長度:
02:19
How to use logic to enable or disable a signal.
Schematic representation of power good signal combination.

Combining Power Good Signals

日期:
2017年 11月 16日

時間長度:
02:20
How to overcome parasitic capacitance when using power good signals.
79 結果
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