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79 結果

Introduction to the RF Sampling Architecture

日期:
2015年 6月 29日

時間長度:
03:21
Introduction to the RF sampling architecture in contrast to traditional direct conversion architectures typically used in existing transceivers.

Engineer It: How to control synthesizer phase noise

日期:
2015年 11月 13日

時間長度:
08:37
A demonstration of how to analyze for synthesizer phase noise in your application

Engineer It: How to design with excellent PLL & VCO noise performance

日期:
2016年 4月 12日

時間長度:
18:18
Simon shows how to optimize your system design with easy design tips to gain excellent PLL & VCO noise performance

Engineer It: How to ehance accuracy in radar applications

日期:
2016年 4月 13日

時間長度:
13:54
Simon explains how to enhance accuracy in radar applications using TI's RF Synthesizers

ADC32RF80: RF Sampling Telecom Receiver Quick-Start

日期:
2016年 5月 15日

時間長度:
07:49
The ADC32RF80 telecom receiver is a dual channel, 14-bit, 3-GSPS ADC with integrated dual Digital Down Converter. This video shows how to use the EVM/software.
Advanced Phase Synchronization Capabilities with Multiple RF PLLs using TI's LMX2594

Advanced Phase Synchronization Capabiliites with Multiple RF PLLs using TI's LMX2594

日期:
2017年 4月 19日

時間長度:
07:08
Watch Nadeem demonstrate advanced phase synchronization capabilities with multiple RF PLLs using TI's high performance LMX2594.

Get Your Clocks in Sync: Hardware Setup

日期:
2017年 8月 14日

時間長度:
02:31
This video demonstrates DEV_CLK skew between two clock outputs of the clocking reference design and the analog channel to channel skew between 2 ADC12DJ3200EVMs

Get Your Clocks in Sync: Software Setup

日期:
2017年 8月 7日

時間長度:
04:20
This video demonstrates the software setup of the Multi-Channel JESD204B 15 GHz Clocking Reference Design for DSO, Radar and 5G Wireless Testers

Get Your Clocks in Sync for JESD204B Data Converters

日期:
2017年 9月 6日

時間長度:
19:17
This video will explore a reference design that shows how to synchronize multiple high-speed JESD204B data converters.

TI 高精度实验室 - 放大器系列

TI 高精度实验室 (TI Precision Labs)

Webinar - What you need to know about Clock Generators, Buffers and RF Synthesizers

日期:
2018年 6月 27日

時間長度:
54:17
Want to learn more about Clock Generators and Buffers ? You're in the right place!

Synchronization of High Speed Multichannel JESD204B Compliant Clocks Part 1

日期:
2018年 7月 17日

時間長度:
07:50
Learn about the high speed multi-channel clocking requirements and challenges.

Synchronization of High Speed Multichannel JESD204B Compliant Clocks Part 3

日期:
2018年 7月 25日

時間長度:
11:22
Learn about the high channel count clocking solution.

Getting started with the AFE74xx RF-sampling transceiver

Quickly evaluate the AFE7444 and/or AFE7422 RF-sampling transceiver with this series of how to videos.

Selecting the right configuration mode with the AFE74xx EVM

日期:
2019年 3月 1日

時間長度:
03:27
Learn how to select the desired mode to configure the AFE.

Hardware setup for internal PLL operation with the AFE74xx EVM

日期:
2019年 3月 1日

時間長度:
02:42
Learn how to set up the hardware for internal PLL clock operation.

How to configure the AFE74xx DAC in Mode 4 using the internal PLL

日期:
2019年 3月 1日

時間長度:
04:55
Learn how to configure the DAC in mode 4 with the AFE74xx EVM

How to configure the AFE74xx ADC in Mode 4 using the internal PLL

日期:
2019年 3月 1日

時間長度:
02:33
Learn how to capture with the ADC in mode 4 with the AFE74xx EVM.

How to configure the AFE74xx EVM in transceiver mode

日期:
2019年 3月 4日

時間長度:
02:03
Learn how to operate the AFE74xx EVM in transceiver mode.

Hardware setup for external clock operation with the AFE74xx EVM

日期:
2019年 3月 4日

時間長度:
03:09
Learn how to set up the hardware to configure the AFE74xx EVM, in mode 4, using an external clock.
79 結果
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