電子郵件

Understanding Clock Jitter Impact to ADC SNR

描述

2015年 7月 21日

This video discusses the sampling clock phase noise performance and how its performance over frequency offset impacts the GSPS ADC SNR performance.

其他資訊

Check out TI Design: TIDA-00479

This course is also a part of the following series

Date: 七月21日2015年
Date: 七月21日2015年
arrow-topclosedeletedownloadmenusearchsortingArrowszoom-inzoom-out arrow-downarrow-uparrowCircle-leftarrowCircle-rightblockDiagramcalculatorcalendarchatBubble-doublechatBubble-personchatBubble-singlecheckmark-circlechevron-downchevron-leftchevron-rightchevron-upchipclipboardclose-circlecrossReferencedashdocument-genericdocument-pdfAcrobatdocument-webevaluationModuleglobehistoryClockinfo-circlelistlockmailmyTIonlineDataSheetpersonphonequestion-circlereferenceDesignshoppingCartstartoolsvideoswarningwiki